TY - GEN
T1 - FCP-LLM
T2 - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025
AU - Lin, Zhuofan
AU - Guo, Zixian
AU - Wang, Chao
AU - Zheng, Ruixin
AU - Ji, Yuxin
AU - Lim, Yang Wei
AU - Zhang, Yuhang
AU - Rokhani, Fakhrul Zaman
AU - Li, Yongfu
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - During the design process of digital integrated circuits, high-quality coverpoint plan plays a crucial role, as it guides the verification process. This challenging task is accomplished by experienced engineers who consume a massive amount of time to extract critical information from design specifications. In this work, we present the FCP-LLM framework that is designed to understand both design specifications and Hardware Description Language (HDL) code to focus on extracting critical edges of designs' ports. It consists of three main components: CP-Generator for creating coverpoint plans, CP-Reviewer for refining the plans, and SV-Coder for generating SystemVerilog code. It has been evaluated with a series of benchmark circuits, comprising 74X-Series circuits and custom digital designs. Our experimental results show that FCP-LLM outperforms the baseline work with an average improvement of exceeding 300%, demonstrating a better balance between effectiveness and redundancy in coverpoint plan generation.
AB - During the design process of digital integrated circuits, high-quality coverpoint plan plays a crucial role, as it guides the verification process. This challenging task is accomplished by experienced engineers who consume a massive amount of time to extract critical information from design specifications. In this work, we present the FCP-LLM framework that is designed to understand both design specifications and Hardware Description Language (HDL) code to focus on extracting critical edges of designs' ports. It consists of three main components: CP-Generator for creating coverpoint plans, CP-Reviewer for refining the plans, and SV-Coder for generating SystemVerilog code. It has been evaluated with a series of benchmark circuits, comprising 74X-Series circuits and custom digital designs. Our experimental results show that FCP-LLM outperforms the baseline work with an average improvement of exceeding 300%, demonstrating a better balance between effectiveness and redundancy in coverpoint plan generation.
KW - Design Verification
KW - Functional Coverpoint
KW - Large Language Model
UR - https://www.scopus.com/pages/publications/105035391002
U2 - 10.1109/APCCAS67402.2025.11377100
DO - 10.1109/APCCAS67402.2025.11377100
M3 - 会议稿件
AN - SCOPUS:105035391002
T3 - Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025
BT - Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 12 October 2025 through 15 October 2025
ER -