Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology

Lijie Sun; Ganbing Shang; Linlin Liu; Jia Cheng; Ao Guo; Zheng Ren; Shaojian Hu; Shoumian Chen; Yuhang Zhao; Mansun Chan; Long Zhang; Xiaojin Li; Yanling Shi

doi:10.1016/j.sse.2015.05.033

Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology

Lijie Sun, Ganbing Shang, Linlin Liu, Jia Cheng, Ao Guo, Zheng Ren, Shaojian Hu, Shoumian Chen, Yuhang Zhao, Mansun Chan, Long Zhang, Xiaojin Li, Yanling Shi

School of Communication and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance (C_f) separated from gate-to-contact capacitance (C_co), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as C_f and C_co of MOSFET. To separate C_f and C_co, novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of C_f with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent C_f in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node.

Original language	English
Pages (from-to)	118-122
Number of pages	5
Journal	Solid-State Electronics
Volume	111
DOIs	https://doi.org/10.1016/j.sse.2015.05.033
State	Published - 13 Jun 2015

Keywords

Contact to contact space
Contact to poly space
Gate-to-contact capacitance
Gate-to-source/drain fringing capacitance
Layout-dependent
SPICE model

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10.1016/j.sse.2015.05.033

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@article{f1f55c11eb544f50960d29c09a029d17,

title = "Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology",

abstract = "In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance (Cf) separated from gate-to-contact capacitance (Cco), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as Cf and Cco of MOSFET. To separate Cf and Cco, novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of Cf with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5\%. The extraction and modeling of the layout-dependent Cf in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node.",

keywords = "Contact to contact space, Contact to poly space, Gate-to-contact capacitance, Gate-to-source/drain fringing capacitance, Layout-dependent, SPICE model",

author = "Lijie Sun and Ganbing Shang and Linlin Liu and Jia Cheng and Ao Guo and Zheng Ren and Shaojian Hu and Shoumian Chen and Yuhang Zhao and Mansun Chan and Long Zhang and Xiaojin Li and Yanling Shi",

year = "2015",

month = jun,

day = "13",

doi = "10.1016/j.sse.2015.05.033",

language = "英语",

volume = "111",

pages = "118--122",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Ltd",

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TY - JOUR

T1 - Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology

AU - Sun, Lijie

AU - Shang, Ganbing

AU - Liu, Linlin

AU - Cheng, Jia

AU - Guo, Ao

AU - Ren, Zheng

AU - Hu, Shaojian

AU - Chen, Shoumian

AU - Zhao, Yuhang

AU - Chan, Mansun

AU - Zhang, Long

AU - Li, Xiaojin

AU - Shi, Yanling

PY - 2015/6/13

Y1 - 2015/6/13

N2 - In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance (Cf) separated from gate-to-contact capacitance (Cco), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as Cf and Cco of MOSFET. To separate Cf and Cco, novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of Cf with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent Cf in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node.

AB - In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance (Cf) separated from gate-to-contact capacitance (Cco), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as Cf and Cco of MOSFET. To separate Cf and Cco, novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of Cf with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent Cf in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node.

KW - Contact to contact space

KW - Contact to poly space

KW - Gate-to-contact capacitance

KW - Gate-to-source/drain fringing capacitance

KW - Layout-dependent

KW - SPICE model

UR - https://www.scopus.com/pages/publications/84931274074

U2 - 10.1016/j.sse.2015.05.033

DO - 10.1016/j.sse.2015.05.033

M3 - 文章

AN - SCOPUS:84931274074

SN - 0038-1101

VL - 111

SP - 118

EP - 122

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology

Abstract

Keywords

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