Exploiting process variation for read performance improvement on LDPC based flash memory storage systems

Qiao Li; Liang Shi; Yejia Di; Yajuan Du; Chun J. Xue; Edwin H.M. Sha

doi:10.1109/ICCD.2017.118

Exploiting process variation for read performance improvement on LDPC based flash memory storage systems

Qiao Li
, Liang Shi
, Yejia Di
, Yajuan Du
, Chun J. Xue
, Edwin H.M. Sha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

With the development of bit density and technology scaling, the process variation (PV) has become much severe on NAND flash memory. As PV presents reliability among flash blocks, which causes read performance variation to read data on different blocks. This paper proposes to improve read performance of LDPC based flash memory by exploiting the reliability characteristics of PV. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Then, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability and move read-cold data to blocks with low reliability. Experiment results show that, with negligible overhead, the proposed scheme is able to significantly improve the read performance.

Original language	English
Title of host publication	Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	681-684
Number of pages	4
ISBN (Electronic)	9781538622544
DOIs	https://doi.org/10.1109/ICCD.2017.118
State	Published - 22 Nov 2017
Externally published	Yes
Event	35th IEEE International Conference on Computer Design, ICCD 2017 - Boston, United States Duration: 5 Nov 2017 → 8 Nov 2017

Publication series

Name	Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017

Conference

Conference	35th IEEE International Conference on Computer Design, ICCD 2017
Country/Territory	United States
City	Boston
Period	5/11/17 → 8/11/17

Access to Document

10.1109/ICCD.2017.118

Cite this

Li, Q., Shi, L., Di, Y., Du, Y., Xue, C. J., & Sha, E. H. M. (2017). Exploiting process variation for read performance improvement on LDPC based flash memory storage systems. In Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017 (pp. 681-684). Article 8119291 (Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD.2017.118

Li, Qiao ; Shi, Liang ; Di, Yejia et al. / Exploiting process variation for read performance improvement on LDPC based flash memory storage systems. Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 681-684 (Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017).

@inproceedings{8b77aab730ae45f3a5bb775fb02ac184,

title = "Exploiting process variation for read performance improvement on LDPC based flash memory storage systems",

abstract = "With the development of bit density and technology scaling, the process variation (PV) has become much severe on NAND flash memory. As PV presents reliability among flash blocks, which causes read performance variation to read data on different blocks. This paper proposes to improve read performance of LDPC based flash memory by exploiting the reliability characteristics of PV. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Then, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability and move read-cold data to blocks with low reliability. Experiment results show that, with negligible overhead, the proposed scheme is able to significantly improve the read performance.",

author = "Qiao Li and Liang Shi and Yejia Di and Yajuan Du and Xue, \{Chun J.\} and Sha, \{Edwin H.M.\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 35th IEEE International Conference on Computer Design, ICCD 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2017",

month = nov,

day = "22",

doi = "10.1109/ICCD.2017.118",

language = "英语",

series = "Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "681--684",

booktitle = "Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017",

address = "美国",

}

Li, Q, Shi, L, Di, Y, Du, Y, Xue, CJ & Sha, EHM 2017, Exploiting process variation for read performance improvement on LDPC based flash memory storage systems. in Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017., 8119291, Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017, Institute of Electrical and Electronics Engineers Inc., pp. 681-684, 35th IEEE International Conference on Computer Design, ICCD 2017, Boston, United States, 5/11/17. https://doi.org/10.1109/ICCD.2017.118

Exploiting process variation for read performance improvement on LDPC based flash memory storage systems. / Li, Qiao; Shi, Liang; Di, Yejia et al.
Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 681-684 8119291 (Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Exploiting process variation for read performance improvement on LDPC based flash memory storage systems

AU - Li, Qiao

AU - Shi, Liang

AU - Di, Yejia

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AU - Xue, Chun J.

AU - Sha, Edwin H.M.

PY - 2017/11/22

Y1 - 2017/11/22

N2 - With the development of bit density and technology scaling, the process variation (PV) has become much severe on NAND flash memory. As PV presents reliability among flash blocks, which causes read performance variation to read data on different blocks. This paper proposes to improve read performance of LDPC based flash memory by exploiting the reliability characteristics of PV. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Then, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability and move read-cold data to blocks with low reliability. Experiment results show that, with negligible overhead, the proposed scheme is able to significantly improve the read performance.

AB - With the development of bit density and technology scaling, the process variation (PV) has become much severe on NAND flash memory. As PV presents reliability among flash blocks, which causes read performance variation to read data on different blocks. This paper proposes to improve read performance of LDPC based flash memory by exploiting the reliability characteristics of PV. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Then, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability and move read-cold data to blocks with low reliability. Experiment results show that, with negligible overhead, the proposed scheme is able to significantly improve the read performance.

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T3 - Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017

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Li Q, Shi L, Di Y, Du Y, Xue CJ, Sha EHM. Exploiting process variation for read performance improvement on LDPC based flash memory storage systems. In Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 681-684. 8119291. (Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017). doi: 10.1109/ICCD.2017.118

Exploiting process variation for read performance improvement on LDPC based flash memory storage systems

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