Abstract
As flash memory has better performance than hard disks, it has been widely applied in embedded systems, personal computers, and data centers as storage components. However, endurance and write performance are the two key challenges in the deployment of flash memory. In this paper, with the awareness of errors induced from write operations, endurance, and retention time, a stage-based optimization approach is proposed to improve the write performance and endurance at different usage stages of flash memory. A series of trace-driven simulations show that the proposed approach outperforms a set of state-of-the-art approaches in terms of write performance and lifetime.
| Original language | English |
|---|---|
| Article number | 6740049 |
| Pages (from-to) | 343-355 |
| Number of pages | 13 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 33 |
| Issue number | 3 |
| DOIs | |
| State | Published - Mar 2014 |
| Externally published | Yes |
Keywords
- Endurance error
- error model
- retention error
- smart refresh
- stage optimization
- write error