Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))

Zhitang Song; Daolin Cai; Yan Cheng; Lei Wang; Shilong Lv; Tianjiao Xin; Gaoming Feng

doi:10.1039/d1nr90100a

Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))

Zhitang Song, Daolin Cai, Yan Cheng, Lei Wang, Shilong Lv, Tianjiao Xin, Gaoming Feng

School of Physics and Electronic Science

Research output: Contribution to journal › Comment/debate

Abstract

Correction for '12-state multi-level cell storage implemented in a 128 Mb phase change memory chip' by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

Original language	English
Pages (from-to)	10608-10609
Number of pages	2
Journal	Nanoscale
Volume	13
Issue number	23
DOIs	https://doi.org/10.1039/d1nr90100a
State	Published - 17 Jun 2021

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10.1039/d1nr90100a

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title = "Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))",

abstract = "Correction for '12-state multi-level cell storage implemented in a 128 Mb phase change memory chip' by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.",

author = "Zhitang Song and Daolin Cai and Yan Cheng and Lei Wang and Shilong Lv and Tianjiao Xin and Gaoming Feng",

year = "2021",

month = jun,

day = "17",

doi = "10.1039/d1nr90100a",

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volume = "13",

pages = "10608--10609",

journal = "Nanoscale",

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publisher = "Royal Society of Chemistry",

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T2 - Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))

AU - Song, Zhitang

AU - Cai, Daolin

AU - Cheng, Yan

AU - Wang, Lei

AU - Lv, Shilong

AU - Xin, Tianjiao

AU - Feng, Gaoming

PY - 2021/6/17

Y1 - 2021/6/17

N2 - Correction for '12-state multi-level cell storage implemented in a 128 Mb phase change memory chip' by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

AB - Correction for '12-state multi-level cell storage implemented in a 128 Mb phase change memory chip' by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

UR - https://www.scopus.com/pages/publications/85108741723

U2 - 10.1039/d1nr90100a

DO - 10.1039/d1nr90100a

M3 - 评论/辩论

C2 - 34137760

AN - SCOPUS:85108741723

SN - 2040-3364

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SP - 10608

EP - 10609

JO - Nanoscale

JF - Nanoscale

IS - 23

ER -

Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))

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