Enhanced logic gates and SRAM based on reconfigurable field-effect transistor with asymmetric spacer engineering

In this paper, an early evaluation of reconfigurable field-effect transistor (RFET) with asymmetric spacer engineering in terms of logic cells and static random-access memory (SRAM) is carried out using 3D-TCAD and logical effort theory. The asymmetric underlap channel extension at the drain side (UCED) is demonstrated to be able to increase the on-state saturated current (I_ON). Furthermore, the proposed UCED RFET shows great stability for different spacer materials, compared to the conventional RFET. Though a slight deterioration of the normalized delay in UCED RFET, the propagation delay of UCED structure is still smaller due to the lower intrinsic delay in the transistor level because control gate capacitance reduces in the meantime. RFET with asymmetric spacer engineering is also demonstrated to relax the competition between the read and the write operation in SRAM.