Energy minimization and latency hiding for heterogeneous parallel memory modules

Meikang Qiu, Gang Wu, Jingtong Hu, Wei Che Tseng, Edwin H.M. Sha

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Many high-performance DSP processors employ multi-module on-chip memory to improve performance and power consumption. This paper studies the scheduling and assignment problem that minimizes the total energy while satisfying performance for applications with loops. An algorithm, LSAMEM (Loop Scheduling and Assignment to Minimize Energy for Memory), is proposed. The algorithm attempts to maximum energy saving while satisfying timing constraint with guaranteed probability. The experimental results show that the average improvement on energy-saving is significant by using LSAMEM.

Original languageEnglish
Title of host publicationICPADS '09 - 15th International Conference on Parallel and Distributed Systems
Pages503-510
Number of pages8
DOIs
StatePublished - 2009
Externally publishedYes
Event15th International Conference on Parallel and Distributed Systems, ICPADS '09 - Shenzhen, Guangdong, China
Duration: 8 Dec 200911 Dec 2009

Publication series

NameProceedings of the International Conference on Parallel and Distributed Systems - ICPADS
ISSN (Print)1521-9097

Conference

Conference15th International Conference on Parallel and Distributed Systems, ICPADS '09
Country/TerritoryChina
CityShenzhen, Guangdong
Period8/12/0911/12/09

Keywords

  • Energy minimization
  • Heterogeneous
  • Latency hiding
  • Memory modules
  • Parallel

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