TY - GEN
T1 - Energy-efficient Analog Processing Architecture for Direction of Arrival with Microphone Array
AU - Liu, Changlu
AU - Lan, Tianxiang
AU - Li, Qin
AU - Jia, Kaige
AU - Fan, Yidian
AU - Wu, Xing
AU - Qiao, Fei
AU - Qi, Wei
AU - Liu, Xin Jun
AU - Yang, Huazhong
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Direction of arrival (DOA) is a critical component in the conventional smart acoustic system for navigation, noise canceling hearing aids and so on. However, conventional DOA has encountered power consumption and processing speed bottlenecks dominated by analog-to-digital converter (ADC) and fast fourier transform (FFT). Especially in the always-on applications, the power-hungry ADC and time-consuming FFT take up most of the system's computation cost. We propose a novel processing architecture with analog-domain processing for DOA. The whole processing procedure of DOA is implemented in the analog domain without ADC and frequency-domain transformation. In order to verify the performance of the architecture, we simulate a generic DOA algorithm. Under the CMOS 0.18μm process, the results show the 94.5% reduction in power consumption and 4724× improvement in processing speed compared to conventional digital realization. We simulate the simple task with the direction accuracy of 80.74%, which can be extended to a more complex scenario.
AB - Direction of arrival (DOA) is a critical component in the conventional smart acoustic system for navigation, noise canceling hearing aids and so on. However, conventional DOA has encountered power consumption and processing speed bottlenecks dominated by analog-to-digital converter (ADC) and fast fourier transform (FFT). Especially in the always-on applications, the power-hungry ADC and time-consuming FFT take up most of the system's computation cost. We propose a novel processing architecture with analog-domain processing for DOA. The whole processing procedure of DOA is implemented in the analog domain without ADC and frequency-domain transformation. In order to verify the performance of the architecture, we simulate a generic DOA algorithm. Under the CMOS 0.18μm process, the results show the 94.5% reduction in power consumption and 4724× improvement in processing speed compared to conventional digital realization. We simulate the simple task with the direction accuracy of 80.74%, which can be extended to a more complex scenario.
KW - analog processing architecture
KW - direction of arrival
KW - energy-constrained
KW - source localization
UR - https://www.scopus.com/pages/publications/85072954003
U2 - 10.1109/ISVLSI.2019.00097
DO - 10.1109/ISVLSI.2019.00097
M3 - 会议稿件
AN - SCOPUS:85072954003
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 507
EP - 512
BT - Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PB - IEEE Computer Society
T2 - 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Y2 - 15 July 2019 through 17 July 2019
ER -
