Electro-thermal Investigation on SOI Accumulation Mode Tri-gate LDMOS

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Abstract

An electro-thermal co-optimization has been carried out on silicon-on-insulator (SOI) accumulation mode tri-gate (ATG) LDMOS by TCAD simulation. Internal electric field, temperature distribution, critical heat removal path and the thermal resistance of SOI-ATG LDMOS are investigated, providing deep insights into its self-heating mechanism and thermal-aware design. Besides, the junction depth of source/drain, ambient temperature and boundary thermal resistance are optimized to mitigate the self-heating effect (SHE) in SOI-ATG LDMOS. Furthermore, different trench dielectrics are also compared to achieve an electro-thermal co-optimization of SOI-ATG LDMOS.

Original languageEnglish
Title of host publication2021 6th International Conference on Integrated Circuits and Microsystems, ICICM 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages210-213
Number of pages4
ISBN (Electronic)9781665458863
DOIs
StatePublished - 2021
Event6th International Conference on Integrated Circuits and Microsystems, ICICM 2021 - Nanjing, China
Duration: 22 Oct 202124 Oct 2021

Publication series

Name2021 6th International Conference on Integrated Circuits and Microsystems, ICICM 2021

Conference

Conference6th International Conference on Integrated Circuits and Microsystems, ICICM 2021
Country/TerritoryChina
CityNanjing
Period22/10/2124/10/21

Keywords

  • Co-optimization
  • Electro-thermal simulation
  • SOI-ATG LDMOS
  • Self-heating effect

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