TY - GEN
T1 - DPP-MP
T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
AU - Xu, Yuan
AU - Zhao, Kangjie
AU - Xie, Wangdong
AU - Wu, Guozhen
AU - Huang, Leilei
AU - Shi, Chunqi
AU - Chen, Jinghong
AU - Zhang, Runxi
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Although quadrature digital transmitters (DTXs) are particularly useful in wideband scenarios, the interaction between I and Q paths would lead to a non-negligible distortion. Unfortunately, traditional DPD models have not performed well in solving this kind of distortion. For example, memory polynomial (MP) model uses signal amplitude as the fundamental term which is not accurate enough to solve this issue, while 2-D lookup table (2D-LUT) model requires a large number of entries which leads to significant hardware resource consumption. In view of this, we propose an area-efficient dual-path piecewise memory-polynomial (DPP-MP) model, which improves model accuracy while reducing hardware resource consumption. To further reduce the area cost, the model is pruned to 8 terms only and 4 of them are reused. To reduce the logic delay, a new squared multiplier is proposed to replace the default one, which reduces delay by 13.51% and power consumption by 2.56%. This model achieves 36.86% and 66.98% area optimization compared to MP and 2D-LUT, respectively. When applied to a 9-bit quadrature DTX with a 40 MHz 256-QAM signal, this model improves the error vector magnitude (EVM) from -16.38 dB to -35.89 dB with a target average power (Pavg) of 21.07 dBm.
AB - Although quadrature digital transmitters (DTXs) are particularly useful in wideband scenarios, the interaction between I and Q paths would lead to a non-negligible distortion. Unfortunately, traditional DPD models have not performed well in solving this kind of distortion. For example, memory polynomial (MP) model uses signal amplitude as the fundamental term which is not accurate enough to solve this issue, while 2-D lookup table (2D-LUT) model requires a large number of entries which leads to significant hardware resource consumption. In view of this, we propose an area-efficient dual-path piecewise memory-polynomial (DPP-MP) model, which improves model accuracy while reducing hardware resource consumption. To further reduce the area cost, the model is pruned to 8 terms only and 4 of them are reused. To reduce the logic delay, a new squared multiplier is proposed to replace the default one, which reduces delay by 13.51% and power consumption by 2.56%. This model achieves 36.86% and 66.98% area optimization compared to MP and 2D-LUT, respectively. When applied to a 9-bit quadrature DTX with a 40 MHz 256-QAM signal, this model improves the error vector magnitude (EVM) from -16.38 dB to -35.89 dB with a target average power (Pavg) of 21.07 dBm.
KW - Digital predistortion (DPD)
KW - digital transmitter (DTX)
KW - hardware implementation
KW - linearization
KW - memory polynomial (MP)
KW - quadrature
KW - squared multiplier
UR - https://www.scopus.com/pages/publications/105010604476
U2 - 10.1109/ISCAS56072.2025.11044027
DO - 10.1109/ISCAS56072.2025.11044027
M3 - 会议稿件
AN - SCOPUS:105010604476
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 25 May 2025 through 28 May 2025
ER -