Detecting hardware Trojan through feature extraction in subspace domain

In order to eliminate the challenge and interference of the process variation and noises on existing hardware Trojan detection methods, a novel hardware Trojan detection technique is presented, which can detect tiny hardware Trojan characteristics under large process variation and background noises. First, the hardware Trojan detection problem is mathematically formulated as a feature extraction model. Then, a unified subspace hardware Trojan detection technique is proposed based on time domain constrained estimator and principal component projection. It is proved that the weak hardware Trojan signal can be distinguished from various noise sources through particular subspace projections or reconstructed clean signal analysis. The proposed technique provides a general method for related works to eliminate the impact of process variations and noises. Two sequential hardware Trojans are designed and implemented. Both simulation experiments on ISCAS89 benchmark circuits and hardware validations on FPGA (field programmable gate array) boards show the effectiveness and high sensitivity of the proposed hardware Trojan detection technique.