Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

Yan Zeng; Xiao Jin Li; Jian Qing; Ya Bin Sun; Yan Ling Shi; Ao Guo; Shao Jian Hu

doi:10.1088/1674-1056/26/10/108503

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

Yan Zeng, Xiao Jin Li, Jian Qing, Ya Bin Sun, Yan Ling Shi, Ao Guo, Shao Jian Hu

School of Communication and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps (ΔV_HT) in gate insulator, generated traps (ΔV_OT) in bulk insulator, and interface trap generation (ΔV_IT). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.

Original language	English
Article number	108503
Journal	Chinese Physics B
Volume	26
Issue number	10
DOIs	https://doi.org/10.1088/1674-1056/26/10/108503
State	Published - Oct 2017

Keywords

H locking effect
interface trap
negative bias temperature instability (NBTI)
reaction diffusion (RD)

Access to Document

10.1088/1674-1056/26/10/108503

Cite this

@article{947a22e2d70b40039151e303675d291e,

title = "Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models",

abstract = "The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps (ΔVHT) in gate insulator, generated traps (ΔVOT) in bulk insulator, and interface trap generation (ΔVIT). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.",

keywords = "H locking effect, interface trap, negative bias temperature instability (NBTI), reaction diffusion (RD)",

author = "Yan Zeng and Li, \{Xiao Jin\} and Jian Qing and Sun, \{Ya Bin\} and Shi, \{Yan Ling\} and Ao Guo and Hu, \{Shao Jian\}",

note = "Publisher Copyright: {\textcopyright} 2017 Chinese Physical Society and IOP Publishing Ltd.",

year = "2017",

month = oct,

doi = "10.1088/1674-1056/26/10/108503",

language = "英语",

volume = "26",

journal = "Chinese Physics B",

issn = "1674-1056",

publisher = "IOP Publishing Ltd.",

number = "10",

}

TY - JOUR

T1 - Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

AU - Zeng, Yan

AU - Li, Xiao Jin

AU - Qing, Jian

AU - Sun, Ya Bin

AU - Shi, Yan Ling

AU - Guo, Ao

AU - Hu, Shao Jian

PY - 2017/10

Y1 - 2017/10

N2 - The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps (ΔVHT) in gate insulator, generated traps (ΔVOT) in bulk insulator, and interface trap generation (ΔVIT). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.

AB - The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps (ΔVHT) in gate insulator, generated traps (ΔVOT) in bulk insulator, and interface trap generation (ΔVIT). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.

KW - H locking effect

KW - interface trap

KW - negative bias temperature instability (NBTI)

KW - reaction diffusion (RD)

UR - https://www.scopus.com/pages/publications/85031042450

U2 - 10.1088/1674-1056/26/10/108503

DO - 10.1088/1674-1056/26/10/108503

M3 - 文章

AN - SCOPUS:85031042450

SN - 1674-1056

VL - 26

JO - Chinese Physics B

JF - Chinese Physics B

IS - 10

M1 - 108503

ER -

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this