Design-Technology Co-Optimization of Complementary Field-Effect Transistors with Tree-Type Channel at 3nm Technology Node

At the 3nm technology node, Complementary FET (CFET) has emerged as a key candidate for continued device scaling. This paper proposes a novel CFET with tree-type channel (Tree-CFET), which integrates the vertical stacking advantages of CFET with the enhanced effective channel width. To assess the impact of dimensional parameters of Tree-CFET along the contact gate pitch (CGP) direction, 11 trade-off schemes were developed for design-technology co-optimization (DTCO). Simulation results indicate that, when comparing the ring oscillator (RO) circuit characteristics of Tree-CFET with the target specifications of IMEC's 5 nm, 3 nm, and 2 nm technology nodes, all 11 schemes achieve the PPA performance targets of the 3nm node, with three also meeting the 2nm node requirements. These results highlight the potential of Tree-CFET in enabling future ultra-scaled logic applications.