Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c

Jun Feng Tang; Xiao Jin Li; Gang Zhang; Zong Sheng Lai

doi:10.1109/ICSICT.2012.6467791

Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c

Jun Feng Tang, Xiao Jin Li, Gang Zhang, Zong Sheng Lai

School of Communication and Electronic Engineering

East China Normal University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

In this paper, a 512-point, 2.7 GS/s fast Fourier transform (FFT) processor embedded with mixed-radix multi-path delay-feedback (MRMDF) structure is proposed. To meet the high throughput requirement of IEEE 802.15.3c (WPANs), the architecture of eight parallel data-paths is adopted. Considering the hardware complexity and high performance, 512 point FFT computation is decomposed into radix-2⁵ and radix-2³ so that the number of the multiplications is reduced by 30% comparing with the traditional method. Furthermore, the complex multipliers are also optimized and replaced by a set of constant multipliers. The proposed FFT processor has been implemented using FPGA, and the result shows that the throughput rate (T.R.) up to 2.7GS/s@338MHz can be achieved.

Original language	English
Title of host publication	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs	https://doi.org/10.1109/ICSICT.2012.6467791
State	Published - 2012
Event	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China Duration: 29 Oct 2012 → 1 Nov 2012

Publication series

Name	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Country/Territory	China
City	Xi'an
Period	29/10/12 → 1/11/12

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10.1109/ICSICT.2012.6467791

Cite this

Tang, J. F., Li, X. J., Zhang, G., & Lai, Z. S. (2012). Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings Article 6467791 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2012.6467791

Tang, Jun Feng ; Li, Xiao Jin ; Zhang, Gang et al. / Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c. ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

@inproceedings{5a94d9500e434904b9d3a093bce3057d,

title = "Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c",

abstract = "In this paper, a 512-point, 2.7 GS/s fast Fourier transform (FFT) processor embedded with mixed-radix multi-path delay-feedback (MRMDF) structure is proposed. To meet the high throughput requirement of IEEE 802.15.3c (WPANs), the architecture of eight parallel data-paths is adopted. Considering the hardware complexity and high performance, 512 point FFT computation is decomposed into radix-25 and radix-23 so that the number of the multiplications is reduced by 30\% comparing with the traditional method. Furthermore, the complex multipliers are also optimized and replaced by a set of constant multipliers. The proposed FFT processor has been implemented using FPGA, and the result shows that the throughput rate (T.R.) up to 2.7GS/s@338MHz can be achieved.",

author = "Tang, \{Jun Feng\} and Li, \{Xiao Jin\} and Gang Zhang and Lai, \{Zong Sheng\}",

year = "2012",

doi = "10.1109/ICSICT.2012.6467791",

language = "英语",

isbn = "9781467324724",

series = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

booktitle = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

note = "2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 ; Conference date: 29-10-2012 Through 01-11-2012",

}

Tang, JF, Li, XJ, Zhang, G & Lai, ZS 2012, Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c. in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 6467791, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012, Xi'an, China, 29/10/12. https://doi.org/10.1109/ICSICT.2012.6467791

Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c. / Tang, Jun Feng; Li, Xiao Jin; Zhang, Gang et al.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467791 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c

AU - Tang, Jun Feng

AU - Li, Xiao Jin

AU - Zhang, Gang

AU - Lai, Zong Sheng

PY - 2012

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N2 - In this paper, a 512-point, 2.7 GS/s fast Fourier transform (FFT) processor embedded with mixed-radix multi-path delay-feedback (MRMDF) structure is proposed. To meet the high throughput requirement of IEEE 802.15.3c (WPANs), the architecture of eight parallel data-paths is adopted. Considering the hardware complexity and high performance, 512 point FFT computation is decomposed into radix-25 and radix-23 so that the number of the multiplications is reduced by 30% comparing with the traditional method. Furthermore, the complex multipliers are also optimized and replaced by a set of constant multipliers. The proposed FFT processor has been implemented using FPGA, and the result shows that the throughput rate (T.R.) up to 2.7GS/s@338MHz can be achieved.

AB - In this paper, a 512-point, 2.7 GS/s fast Fourier transform (FFT) processor embedded with mixed-radix multi-path delay-feedback (MRMDF) structure is proposed. To meet the high throughput requirement of IEEE 802.15.3c (WPANs), the architecture of eight parallel data-paths is adopted. Considering the hardware complexity and high performance, 512 point FFT computation is decomposed into radix-25 and radix-23 so that the number of the multiplications is reduced by 30% comparing with the traditional method. Furthermore, the complex multipliers are also optimized and replaced by a set of constant multipliers. The proposed FFT processor has been implemented using FPGA, and the result shows that the throughput rate (T.R.) up to 2.7GS/s@338MHz can be achieved.

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Tang JF, Li XJ, Zhang G, Lai ZS. Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467791. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2012.6467791

Design of high-throughput mixed-radix MDF FFT processor for IEEE 802.11.3c

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