Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application

Ming Wang; Miao Xing Xie; Xiang Long Li; Ya Bin Sun; Xiao Jin Li; Yan Fang Ding; Yan Ling Shi

doi:10.1109/ICSICT49897.2020.9278135

Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application

Ming Wang
, Miao Xing Xie^*
, Xiang Long Li
, Ya Bin Sun
, Xiao Jin Li
, Yan Fang Ding
, Yan Ling Shi

^*Corresponding author for this work

School of Communication and Electronic Engineering

East China Normal University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A wide-range charge pump phase-locked loop (CPPLL) for Sub-1G Internet-of-Things (IoT) application is proposed in this paper. Dual voltage-controlled oscillator (VCO) technique is adopted to achieve wide frequency tuning range. In addition, the Kvcocompensation method is also employed to stabilize Kvcoin the entire frequency tuning range, combined with dual VCO structure. The design has been fabricated in CMOS 0.11 µm technology and the presented PLL achieved a wide frequency tuning range from 54.8MHz to 1.086GHz, with die area of 0.8 mm2. The measured phase noise is-85.92dBc/Hz and-116.23dBc/Hz at 100kHz and 1MHz, respectively, and the measured reference spur is-63dBc at 24MHz.

Original language	English
Title of host publication	2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings
Editors	Shaofeng Yu, Xiaona Zhu, Ting-Ao Tang
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728162355
DOIs	https://doi.org/10.1109/ICSICT49897.2020.9278135
State	Published - 3 Nov 2020
Event	15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Virtual, Kunming, China Duration: 3 Nov 2020 → 6 Nov 2020

Publication series

Name	2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

Conference

Conference	15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020
Country/Territory	China
City	Virtual, Kunming
Period	3/11/20 → 6/11/20

Access to Document

10.1109/ICSICT49897.2020.9278135

Cite this

Wang, M., Xie, M. X., Li, X. L., Sun, Y. B., Li, X. J., Ding, Y. F., & Shi, Y. L. (2020). Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application. In S. Yu, X. Zhu, & T.-A. Tang (Eds.), 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings Article 9278135 (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT49897.2020.9278135

Wang, Ming ; Xie, Miao Xing ; Li, Xiang Long et al. / Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application. 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings. editor / Shaofeng Yu ; Xiaona Zhu ; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings).

@inproceedings{91c61d055db8480295b8b55069d8534e,

title = "Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application",

abstract = "A wide-range charge pump phase-locked loop (CPPLL) for Sub-1G Internet-of-Things (IoT) application is proposed in this paper. Dual voltage-controlled oscillator (VCO) technique is adopted to achieve wide frequency tuning range. In addition, the Kvcocompensation method is also employed to stabilize Kvcoin the entire frequency tuning range, combined with dual VCO structure. The design has been fabricated in CMOS 0.11 µm technology and the presented PLL achieved a wide frequency tuning range from 54.8MHz to 1.086GHz, with die area of 0.8 mm2. The measured phase noise is-85.92dBc/Hz and-116.23dBc/Hz at 100kHz and 1MHz, respectively, and the measured reference spur is-63dBc at 24MHz.",

author = "Ming Wang and Xie, \{Miao Xing\} and Li, \{Xiang Long\} and Sun, \{Ya Bin\} and Li, \{Xiao Jin\} and Ding, \{Yan Fang\} and Shi, \{Yan Ling\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 ; Conference date: 03-11-2020 Through 06-11-2020",

year = "2020",

month = nov,

day = "3",

doi = "10.1109/ICSICT49897.2020.9278135",

language = "英语",

series = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Shaofeng Yu and Xiaona Zhu and Ting-Ao Tang",

booktitle = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",

address = "美国",

}

Wang, M, Xie, MX, Li, XL, Sun, YB , Li, XJ, Ding, YF & Shi, YL 2020, Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application. in S Yu, X Zhu & T-A Tang (eds), 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings., 9278135, 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020, Virtual, Kunming, China, 3/11/20. https://doi.org/10.1109/ICSICT49897.2020.9278135

Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application. / Wang, Ming; Xie, Miao Xing; Li, Xiang Long et al.
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings. ed. / Shaofeng Yu; Xiaona Zhu; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2020. 9278135 (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application

AU - Wang, Ming

AU - Xie, Miao Xing

AU - Li, Xiang Long

AU - Sun, Ya Bin

AU - Li, Xiao Jin

AU - Ding, Yan Fang

AU - Shi, Yan Ling

PY - 2020/11/3

Y1 - 2020/11/3

N2 - A wide-range charge pump phase-locked loop (CPPLL) for Sub-1G Internet-of-Things (IoT) application is proposed in this paper. Dual voltage-controlled oscillator (VCO) technique is adopted to achieve wide frequency tuning range. In addition, the Kvcocompensation method is also employed to stabilize Kvcoin the entire frequency tuning range, combined with dual VCO structure. The design has been fabricated in CMOS 0.11 µm technology and the presented PLL achieved a wide frequency tuning range from 54.8MHz to 1.086GHz, with die area of 0.8 mm2. The measured phase noise is-85.92dBc/Hz and-116.23dBc/Hz at 100kHz and 1MHz, respectively, and the measured reference spur is-63dBc at 24MHz.

AB - A wide-range charge pump phase-locked loop (CPPLL) for Sub-1G Internet-of-Things (IoT) application is proposed in this paper. Dual voltage-controlled oscillator (VCO) technique is adopted to achieve wide frequency tuning range. In addition, the Kvcocompensation method is also employed to stabilize Kvcoin the entire frequency tuning range, combined with dual VCO structure. The design has been fabricated in CMOS 0.11 µm technology and the presented PLL achieved a wide frequency tuning range from 54.8MHz to 1.086GHz, with die area of 0.8 mm2. The measured phase noise is-85.92dBc/Hz and-116.23dBc/Hz at 100kHz and 1MHz, respectively, and the measured reference spur is-63dBc at 24MHz.

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DO - 10.1109/ICSICT49897.2020.9278135

M3 - 会议稿件

AN - SCOPUS:85099185276

T3 - 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

BT - 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

A2 - Yu, Shaofeng

A2 - Zhu, Xiaona

A2 - Tang, Ting-Ao

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

Y2 - 3 November 2020 through 6 November 2020

ER -

Wang M, Xie MX, Li XL, Sun YB , Li XJ, Ding YF et al. Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application. In Yu S, Zhu X, Tang TA, editors, 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9278135. (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings). doi: 10.1109/ICSICT49897.2020.9278135

Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application

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