Design of a Reconfigurable Multifunctional Standard Cell for Engineering Change Order

This brief presents a reconfigurable multifunctional logic standard cell that offers a new design methodology in the engineering change order (ECO) process to reduce the design risks and nonrecurring engineering (NRE) cost and enhance its current performances. Based on the self-dual graph theory, we have implemented multiple logic (XOR, XNOR, NAND, NOR, AND, and OR) functions in a complementary H-bridge standard cell circuit. A dynamic logic architecture is adopted to reduce the operating supply voltage and active area. Fabricated in a 55-nm CMOS technology, the measurement results have validated the functionality of the proposed circuit under 0.3- to 1.2-V supply voltage. The average propagation delay and power consumption are 82 ns and 0.26 nW, respectively, at a supply voltage of 0.3 V and clock frequency of 1 MHz. An ECO flow is developed based on the proposed reconfigurable standard cell. The results indicate that the proposed reconfigurable standard cell reduces the required number of ECO cells by 1.8-3.6 times.