Design of a IF logarithmic amplifier for ASK receiver

  • Yong Gang Tao*
  • , Yong Sheng Xu
  • , Chun Qi Shi
  • , Wei Jin
  • , Hui Yu
  • , Liang Hong
  • , Yong Li
  • , Zong Sheng Lai
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A bipolar logarithmic intermediate-frequency (IF) amplifier with received signal strength indicator (RSSI) circuit for ASK Receiver is presented. The amplifier realizes a piecewise approximation to an exact logarithmic response. In the demodulating Log Amplifiers, a special architecture of RSSI is proposed. There are five stages in Log amplifiers. Each consists of a limiter amplifier and a gm cell. A 90 dB input dynamic range within ±1 dB linearity is achieved.

Original languageEnglish
Pages (from-to)44-47
Number of pages4
JournalDianzi Qijian/Journal of Electron Devices
Volume29
Issue number1
StatePublished - Mar 2006

Keywords

  • IF amplifier
  • Log amplifier

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