Abstract
This paper presents the derivation of an operational semantics from a denotational semantics for a subset of the widely used hardware description language Verilog. Our aim is to build equivalence between the operational and denotational semantics. We propose a discrete denotational semantic model for Verilog. A phase semantics is provided for each type of transition in order to derive the operational semantics.
| Original language | English |
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| Pages | 177-184 |
| Number of pages | 8 |
| State | Published - 2001 |
| Externally published | Yes |
| Event | 8th Asia Pacific Software Engineering Conference APSEC'2001 - Macao, China Duration: 4 Dec 2001 → 7 Dec 2001 |
Conference
| Conference | 8th Asia Pacific Software Engineering Conference APSEC'2001 |
|---|---|
| Country/Territory | China |
| City | Macao |
| Period | 4/12/01 → 7/12/01 |