Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems

Lei Yang; Weichen Liu; Nan Guan; Mengquan Li; Peng Chen; Edwin H.M. Sha

doi:10.1109/ASPDAC.2017.7858371

Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems

Lei Yang
, Weichen Liu^*
, Nan Guan
, Mengquan Li
, Peng Chen
, Edwin H.M. Sha

^*Corresponding author for this work

Chongqing University
Hong Kong Polytechnic University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

ARM's big. LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) has enabled energy-efficient solutions in the dark silicon era. System-level techniques activate nonadjacent cores to eliminate chip thermal hotspot. However, it unexpectedly increases communication delay due to longer distance in network architectures, and in turn degrades application performance and system energy efficiency. In this paper, we present a novel hierarchical hardware-software collaborated approach to address the performance/temperature conflict in dark silicon many-core systems. Optimizations on interprocessor communication, application performance, chip temperature and energy consumption are well isolated and addressed in different phases. Evaluation results show that on average 22.57% reduction of communication latency, 23.04% improvement on energy efficiency and 6.11°C reduction of chip peak temperature are achieved compared with state-of-the-art techniques.

Original language	English
Title of host publication	2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	494-499
Number of pages	6
ISBN (Electronic)	9781509015580
DOIs	https://doi.org/10.1109/ASPDAC.2017.7858371
State	Published - 16 Feb 2017
Externally published	Yes
Event	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 - Chiba, Japan Duration: 16 Jan 2017 → 19 Jan 2017

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Country/Territory	Japan
City	Chiba
Period	16/01/17 → 19/01/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/ASPDAC.2017.7858371

Cite this

Yang, L., Liu, W., Guan, N., Li, M., Chen, P., & Sha, E. H. M. (2017). Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 (pp. 494-499). Article 7858371 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2017.7858371

Yang, Lei ; Liu, Weichen ; Guan, Nan et al. / Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems. 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 494-499 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{6be4365bcb0740b795230ce43ffec1ce,

title = "Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems",

abstract = "ARM's big. LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) has enabled energy-efficient solutions in the dark silicon era. System-level techniques activate nonadjacent cores to eliminate chip thermal hotspot. However, it unexpectedly increases communication delay due to longer distance in network architectures, and in turn degrades application performance and system energy efficiency. In this paper, we present a novel hierarchical hardware-software collaborated approach to address the performance/temperature conflict in dark silicon many-core systems. Optimizations on interprocessor communication, application performance, chip temperature and energy consumption are well isolated and addressed in different phases. Evaluation results show that on average 22.57\% reduction of communication latency, 23.04\% improvement on energy efficiency and 6.11°C reduction of chip peak temperature are achieved compared with state-of-the-art techniques.",

author = "Lei Yang and Weichen Liu and Nan Guan and Mengquan Li and Peng Chen and Sha, \{Edwin H.M.\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 ; Conference date: 16-01-2017 Through 19-01-2017",

year = "2017",

month = feb,

day = "16",

doi = "10.1109/ASPDAC.2017.7858371",

language = "英语",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "494--499",

booktitle = "2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017",

address = "美国",

}

Yang, L, Liu, W, Guan, N, Li, M, Chen, P & Sha, EHM 2017, Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems. in 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017., 7858371, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 494-499, 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, 16/01/17. https://doi.org/10.1109/ASPDAC.2017.7858371

Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems. / Yang, Lei; Liu, Weichen; Guan, Nan et al.
2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 494-499 7858371 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems

AU - Yang, Lei

AU - Liu, Weichen

AU - Guan, Nan

AU - Li, Mengquan

AU - Chen, Peng

AU - Sha, Edwin H.M.

PY - 2017/2/16

Y1 - 2017/2/16

N2 - ARM's big. LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) has enabled energy-efficient solutions in the dark silicon era. System-level techniques activate nonadjacent cores to eliminate chip thermal hotspot. However, it unexpectedly increases communication delay due to longer distance in network architectures, and in turn degrades application performance and system energy efficiency. In this paper, we present a novel hierarchical hardware-software collaborated approach to address the performance/temperature conflict in dark silicon many-core systems. Optimizations on interprocessor communication, application performance, chip temperature and energy consumption are well isolated and addressed in different phases. Evaluation results show that on average 22.57% reduction of communication latency, 23.04% improvement on energy efficiency and 6.11°C reduction of chip peak temperature are achieved compared with state-of-the-art techniques.

AB - ARM's big. LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) has enabled energy-efficient solutions in the dark silicon era. System-level techniques activate nonadjacent cores to eliminate chip thermal hotspot. However, it unexpectedly increases communication delay due to longer distance in network architectures, and in turn degrades application performance and system energy efficiency. In this paper, we present a novel hierarchical hardware-software collaborated approach to address the performance/temperature conflict in dark silicon many-core systems. Optimizations on interprocessor communication, application performance, chip temperature and energy consumption are well isolated and addressed in different phases. Evaluation results show that on average 22.57% reduction of communication latency, 23.04% improvement on energy efficiency and 6.11°C reduction of chip peak temperature are achieved compared with state-of-the-art techniques.

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DO - 10.1109/ASPDAC.2017.7858371

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BT - 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017

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Yang L, Liu W, Guan N, Li M, Chen P, Sha EHM. Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 494-499. 7858371. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2017.7858371

Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems

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