TY - GEN
T1 - Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems
AU - Yang, Lei
AU - Liu, Weichen
AU - Guan, Nan
AU - Li, Mengquan
AU - Chen, Peng
AU - Sha, Edwin H.M.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/2/16
Y1 - 2017/2/16
N2 - ARM's big. LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) has enabled energy-efficient solutions in the dark silicon era. System-level techniques activate nonadjacent cores to eliminate chip thermal hotspot. However, it unexpectedly increases communication delay due to longer distance in network architectures, and in turn degrades application performance and system energy efficiency. In this paper, we present a novel hierarchical hardware-software collaborated approach to address the performance/temperature conflict in dark silicon many-core systems. Optimizations on interprocessor communication, application performance, chip temperature and energy consumption are well isolated and addressed in different phases. Evaluation results show that on average 22.57% reduction of communication latency, 23.04% improvement on energy efficiency and 6.11°C reduction of chip peak temperature are achieved compared with state-of-the-art techniques.
AB - ARM's big. LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) has enabled energy-efficient solutions in the dark silicon era. System-level techniques activate nonadjacent cores to eliminate chip thermal hotspot. However, it unexpectedly increases communication delay due to longer distance in network architectures, and in turn degrades application performance and system energy efficiency. In this paper, we present a novel hierarchical hardware-software collaborated approach to address the performance/temperature conflict in dark silicon many-core systems. Optimizations on interprocessor communication, application performance, chip temperature and energy consumption are well isolated and addressed in different phases. Evaluation results show that on average 22.57% reduction of communication latency, 23.04% improvement on energy efficiency and 6.11°C reduction of chip peak temperature are achieved compared with state-of-the-art techniques.
UR - https://www.scopus.com/pages/publications/85015262901
U2 - 10.1109/ASPDAC.2017.7858371
DO - 10.1109/ASPDAC.2017.7858371
M3 - 会议稿件
AN - SCOPUS:85015262901
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 494
EP - 499
BT - 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Y2 - 16 January 2017 through 19 January 2017
ER -
