TY - GEN
T1 - D2D-LLM+
T2 - 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2025
AU - Tang, Ruoyu
AU - Wang, Chao
AU - Yap, Jiajun
AU - Guo, Zixian
AU - Zhang, Yuhang
AU - Zhao, Jian
AU - Yin, Minghui
AU - Li, Zhiqiang
AU - Rokhani, Fakhrul Zaman
AU - Li, Yongfu
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - The accurate and consistent translation of design rules/manuals into machine-readable Design Rule Check (DRC) formats is critical for ensuring the manufacturability and reliability of integrated circuits. However, the process is often hindered by inconsistencies in the language and structure of design rules/manuals, which lead to errors in DRC implementation across various Electronic Design Automation (EDA) tools. This paper presents a new tool D2D-LLM+, that leverages large language models to automate the translation of DRC codes into design rules/manuals compatible with leading EDA tools such as Mentor, Cadence, Synopsys, and open-source platforms like KLayout and Magic. Key challenges addressed include the hallucination and stability issues caused by inconsistent terminology and ambiguous language, as well as the visualization challenges of design rules. Additionally, we explore strategies to enhance large language models (LLM) learning through dataset augmentation, improving result accuracy, and increasing the stability and efficiency of LLM models through various prompt engineering techniques. Through extensive validation, we demonstrate the effectiveness of our approach in reducing errors and streamlining the DRC workflow, paving the way for more reliable IC design processes.
AB - The accurate and consistent translation of design rules/manuals into machine-readable Design Rule Check (DRC) formats is critical for ensuring the manufacturability and reliability of integrated circuits. However, the process is often hindered by inconsistencies in the language and structure of design rules/manuals, which lead to errors in DRC implementation across various Electronic Design Automation (EDA) tools. This paper presents a new tool D2D-LLM+, that leverages large language models to automate the translation of DRC codes into design rules/manuals compatible with leading EDA tools such as Mentor, Cadence, Synopsys, and open-source platforms like KLayout and Magic. Key challenges addressed include the hallucination and stability issues caused by inconsistent terminology and ambiguous language, as well as the visualization challenges of design rules. Additionally, we explore strategies to enhance large language models (LLM) learning through dataset augmentation, improving result accuracy, and increasing the stability and efficiency of LLM models through various prompt engineering techniques. Through extensive validation, we demonstrate the effectiveness of our approach in reducing errors and streamlining the DRC workflow, paving the way for more reliable IC design processes.
KW - Design Rule Checking
KW - Electronic Design Automation
KW - Large Language Model
KW - Prompt Engineering
KW - Semiconductor Industry
UR - https://www.scopus.com/pages/publications/105018799632
U2 - 10.1109/AICAS64808.2025.11173119
DO - 10.1109/AICAS64808.2025.11173119
M3 - 会议稿件
AN - SCOPUS:105018799632
T3 - AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings
BT - AICAS 2025 - 2025 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 28 April 2025 through 30 April 2025
ER -