Coverage-driven automatic test generation for UML activity diagrams

Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

33 Scopus citations

Abstract

Due to the increasing complexity of today's embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded system design as a system level specification. One of the major bottlenecks in the validation of UML activity diagrams is the lack of automated techniques for directed test generation. This paper proposes an automated test generation approach for the UML activity diagrams. The contribution of this paper is the use of specification coverage to generate properties as well as design models to enable directed test generation using model checking. Our experimental results demonstrate that our approach can drastically reduce the validation effort in both specification and implementation levels.

Original languageEnglish
Title of host publicationGLSVLSI 2008
Subtitle of host publicationProceedings of the 2008 ACM Great Lakes Symposium on VLSI
Pages139-142
Number of pages4
DOIs
StatePublished - 2008
Externally publishedYes
EventGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States
Duration: 4 Mar 20086 Mar 2008

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

ConferenceGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
Country/TerritoryUnited States
CityOrlando, FL
Period4/03/086/03/08

Keywords

  • Test generation
  • UML activity diagrams

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