Computation and data transfer co-scheduling for interconnection bus minimization

High Instruction-Level-Parallelism in DSP and media applications demands highly clustered architecture. It is challenge to design an efficient, flexible yet cost saving interconnection network to satisfy the rapid increasing inter-cluster data transfer needs. This paper presents a computation and data transfer co-scheduling technique to minimize the number of partially connected interconnection buses required for a given embedded application while minimizing its schedule length. Previous researches in this area focused on scheduling computations to minimize the number of inter-cluster data transfers. The proposed co-scheduling technique in this paper not only schedules computations to reduce the number of inter-cluster data transfers, but also schedules inter- cluster data transfers to minimize the number of required partially connected buses for inter-cluster connection network. Experimental results indicate that 39.4% fewer buses required compared to current best known technique while achieving the same schedule length minimization.