TY - JOUR
T1 - Complete Formal Verification of the PSTM Transaction Scheduler
AU - Popovic, Miroslav
AU - Popovic, Marko
AU - Kordic, Branislav
AU - Zhu, Huibiao
N1 - Publisher Copyright:
© 2023, ComSIS Consortium. All rights reserved.
PY - 2023/1
Y1 - 2023/1
N2 - State of the art formal verification is based on formal methods and its goal is proving given correctness properties. For example, a PSTM scheduler was modeled in CSP in order to prove deadlock-freeness and starvation-freeness. However, as this paper shows, using solely formal methods is not sufficient. Therefore, in this paper we propose a complete formal verification of trustworthy software, which jointly uses formal verification and formal model testing. As an example, we first test the previous CSP model of PSTM transaction scheduler by comparing the model checker PAT results with the manually derived expected results, for the given test workloads. Next, according to the results of this testing, we correct and extend the CSP model. Finally, using PAT results for the new CSP model, we analyze the performance of the PSTM online transaction scheduling algorithms from the perspective of the relative speedup.
AB - State of the art formal verification is based on formal methods and its goal is proving given correctness properties. For example, a PSTM scheduler was modeled in CSP in order to prove deadlock-freeness and starvation-freeness. However, as this paper shows, using solely formal methods is not sufficient. Therefore, in this paper we propose a complete formal verification of trustworthy software, which jointly uses formal verification and formal model testing. As an example, we first test the previous CSP model of PSTM transaction scheduler by comparing the model checker PAT results with the manually derived expected results, for the given test workloads. Next, according to the results of this testing, we correct and extend the CSP model. Finally, using PAT results for the new CSP model, we analyze the performance of the PSTM online transaction scheduling algorithms from the perspective of the relative speedup.
KW - Formal Verification
KW - Process Algebra
KW - Python
KW - Software Transactional Memory
KW - Transaction Scheduling
UR - https://www.scopus.com/pages/publications/85149121645
U2 - 10.2298/CSIS210908058P
DO - 10.2298/CSIS210908058P
M3 - 文章
AN - SCOPUS:85149121645
SN - 1820-0214
VL - 29
SP - 307
EP - 327
JO - Computer Science and Information Systems
JF - Computer Science and Information Systems
IS - 1
ER -