Compiler-assisted refresh minimization for volatile STT-RAM cache

Qingan Li; Jianhua Li; Liang Shi; Chun Jason Xue; Yiran Chen; Yanxiang He

doi:10.1109/ASPDAC.2013.6509608

Compiler-assisted refresh minimization for volatile STT-RAM cache

Qingan Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yiran Chen, Yanxiang He

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

Original language	English
Title of host publication	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
Pages	273-278
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2013.6509608
State	Published - 2013
Externally published	Yes
Event	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan Duration: 22 Jan 2013 → 25 Jan 2013

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
Country/Territory	Japan
City	Yokohama
Period	22/01/13 → 25/01/13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ASPDAC.2013.6509608

Cite this

@inproceedings{06d17f622bc3449d8ed381be3dffa3b0,

title = "Compiler-assisted refresh minimization for volatile STT-RAM cache",

abstract = "Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3\%, and reduce the dynamic energy consumption by 27.6\%.",

author = "Qingan Li and Jianhua Li and Liang Shi and Xue, \{Chun Jason\} and Yiran Chen and Yanxiang He",

year = "2013",

doi = "10.1109/ASPDAC.2013.6509608",

language = "英语",

isbn = "9781467330299",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "273--278",

booktitle = "2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013",

note = "2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 ; Conference date: 22-01-2013 Through 25-01-2013",

}

Li, Q, Li, J, Shi, L, Xue, CJ, Chen, Y & He, Y 2013, Compiler-assisted refresh minimization for volatile STT-RAM cache. in 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013., 6509608, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 273-278, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, 22/01/13. https://doi.org/10.1109/ASPDAC.2013.6509608

Compiler-assisted refresh minimization for volatile STT-RAM cache. / Li, Qingan; Li, Jianhua; Shi, Liang et al.
2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. 2013. p. 273-278 6509608 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Compiler-assisted refresh minimization for volatile STT-RAM cache

AU - Li, Qingan

AU - Li, Jianhua

AU - Shi, Liang

AU - Xue, Chun Jason

AU - Chen, Yiran

AU - He, Yanxiang

PY - 2013

Y1 - 2013

N2 - Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

AB - Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

UR - https://www.scopus.com/pages/publications/84877725977

U2 - 10.1109/ASPDAC.2013.6509608

DO - 10.1109/ASPDAC.2013.6509608

M3 - 会议稿件

AN - SCOPUS:84877725977

SN - 9781467330299

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 273

EP - 278

BT - 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013

T2 - 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013

Y2 - 22 January 2013 through 25 January 2013

ER -

Compiler-assisted refresh minimization for volatile STT-RAM cache

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