TY - JOUR
T1 - Compact Modeling of Process Variation and Reliability Predictions for Nanosheet Gate-All-Around FET
AU - Jin, Mengge
AU - Wang, Chao
AU - Xu, Siyi
AU - Shen, Yang
AU - Zhang, Yuhang
AU - Ye, Bingyi
AU - Chen, Shaoqiang
AU - Dong, Xinyu
AU - Lu, Fei
AU - Liu, Ziyu
AU - Li, Xiaojin
AU - Shi, Yanling
AU - Sun, Yabin
N1 - Publisher Copyright:
© 2001-2011 IEEE.
PY - 2025/9
Y1 - 2025/9
N2 - In this work, a semi-analytical compact model is developed to quantify the impact of random process variations on nanosheet field-effect transistors (NSFETs) at the 3nm technology node. Three primary sources of variability work function variation (WFV), line width roughness (LWR), and gate edge roughness (GER) are systematically analyzed. By extracting and calibrating empirical parameters, the proposed model accurately captures the statistical trends of process-induced fluctuations across a broad range of conditions. The model is integrated into the BSIM-CMG framework for circuit-level variability assessment, enabling comprehensive evaluation of performance deviations. Simulation results indicate that WFV dominates the overall reliability degradation, leading to energy variations from -12% to +24%. This study provides a refined predictive framework for assessing process-induced reliability risks and optimizing circuit design in advanced semiconductor technologies.
AB - In this work, a semi-analytical compact model is developed to quantify the impact of random process variations on nanosheet field-effect transistors (NSFETs) at the 3nm technology node. Three primary sources of variability work function variation (WFV), line width roughness (LWR), and gate edge roughness (GER) are systematically analyzed. By extracting and calibrating empirical parameters, the proposed model accurately captures the statistical trends of process-induced fluctuations across a broad range of conditions. The model is integrated into the BSIM-CMG framework for circuit-level variability assessment, enabling comprehensive evaluation of performance deviations. Simulation results indicate that WFV dominates the overall reliability degradation, leading to energy variations from -12% to +24%. This study provides a refined predictive framework for assessing process-induced reliability risks and optimizing circuit design in advanced semiconductor technologies.
KW - Process fluctuation
KW - compact model
KW - gate edge roughness (GER)
KW - line width roughness (LWR)
KW - nanosheet field effect transistor (NSFET)
KW - work-function variation (WFV)
UR - https://www.scopus.com/pages/publications/105010876991
U2 - 10.1109/TDMR.2025.3589379
DO - 10.1109/TDMR.2025.3589379
M3 - 文章
AN - SCOPUS:105010876991
SN - 1530-4388
VL - 25
SP - 707
EP - 713
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
IS - 3
ER -