Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory

Yi He; Chun Jason Xue; Cathy Qun Xu; Edwin H.M. Sha

doi:10.1109/ASPDAC.2010.5419914

Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory

Yi He^*
, Chun Jason Xue
, Cathy Qun Xu
, Edwin H.M. Sha

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

An MPSoC system usually consists of a number of processors, a memory hierarchy and a communication mechanism between processors. Because of the gap between the constantly increasing processor speed and slower memory access, how to utilize the memory subsystem more efficiently has become a critical issue for improving the overall system performance. To address this problem, two algorithms are proposed in this paper. The first one uses the integer linear programming method so that the memory access cost is minimized while tasks are scheduled in as short a time as possible. The second one is a heuristic algorithm which can achieve close to optimum results with linear running time. The experimental results show that the memory access cost can be reduced up to 56% comparing to LIST scheduling.

Original language	English
Title of host publication	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages	95-100
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419914
State	Published - 2010
Externally published	Yes
Event	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China Duration: 18 Jan 2010 → 21 Jan 2010

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Country/Territory	Taiwan, Province of China
City	Taipei
Period	18/01/10 → 21/01/10

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10.1109/ASPDAC.2010.5419914

Cite this

He, Y., Xue, C. J., Xu, C. Q., & Sha, E. H. M. (2010). Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (pp. 95-100). Article 5419914 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419914

@inproceedings{0288a1ca5c654eb088c917f1de53a829,

title = "Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory",

abstract = "An MPSoC system usually consists of a number of processors, a memory hierarchy and a communication mechanism between processors. Because of the gap between the constantly increasing processor speed and slower memory access, how to utilize the memory subsystem more efficiently has become a critical issue for improving the overall system performance. To address this problem, two algorithms are proposed in this paper. The first one uses the integer linear programming method so that the memory access cost is minimized while tasks are scheduled in as short a time as possible. The second one is a heuristic algorithm which can achieve close to optimum results with linear running time. The experimental results show that the memory access cost can be reduced up to 56\% comparing to LIST scheduling.",

author = "Yi He and Xue, \{Chun Jason\} and Xu, \{Cathy Qun\} and Sha, \{Edwin H.M.\}",

year = "2010",

doi = "10.1109/ASPDAC.2010.5419914",

language = "英语",

isbn = "9781424457656",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "95--100",

booktitle = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010",

note = "2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 ; Conference date: 18-01-2010 Through 21-01-2010",

}

He, Y, Xue, CJ, Xu, CQ & Sha, EHM 2010, Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory. in 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010., 5419914, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 95-100, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, Province of China, 18/01/10. https://doi.org/10.1109/ASPDAC.2010.5419914

Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory. / He, Yi; Xue, Chun Jason; Xu, Cathy Qun et al.
2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. 2010. p. 95-100 5419914 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory

AU - He, Yi

AU - Xue, Chun Jason

AU - Xu, Cathy Qun

AU - Sha, Edwin H.M.

PY - 2010

Y1 - 2010

N2 - An MPSoC system usually consists of a number of processors, a memory hierarchy and a communication mechanism between processors. Because of the gap between the constantly increasing processor speed and slower memory access, how to utilize the memory subsystem more efficiently has become a critical issue for improving the overall system performance. To address this problem, two algorithms are proposed in this paper. The first one uses the integer linear programming method so that the memory access cost is minimized while tasks are scheduled in as short a time as possible. The second one is a heuristic algorithm which can achieve close to optimum results with linear running time. The experimental results show that the memory access cost can be reduced up to 56% comparing to LIST scheduling.

AB - An MPSoC system usually consists of a number of processors, a memory hierarchy and a communication mechanism between processors. Because of the gap between the constantly increasing processor speed and slower memory access, how to utilize the memory subsystem more efficiently has become a critical issue for improving the overall system performance. To address this problem, two algorithms are proposed in this paper. The first one uses the integer linear programming method so that the memory access cost is minimized while tasks are scheduled in as short a time as possible. The second one is a heuristic algorithm which can achieve close to optimum results with linear running time. The experimental results show that the memory access cost can be reduced up to 56% comparing to LIST scheduling.

UR - https://www.scopus.com/pages/publications/77951215090

U2 - 10.1109/ASPDAC.2010.5419914

DO - 10.1109/ASPDAC.2010.5419914

M3 - 会议稿件

AN - SCOPUS:77951215090

SN - 9781424457656

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 95

EP - 100

BT - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010

T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010

Y2 - 18 January 2010 through 21 January 2010

ER -

Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory

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