Co-Optimization Between Static and Switching Characteristics of LDMOS With p-Type Trapezoidal Gate Embedded in Drift Region

— In this article, a novel p-type trapezoidal gate (PTG) lateral double-diffused MOSFET (LDMOS) is proposed and investigated by the 3-D TCAD simulation. The results reveal that the PTG LDMOS boasts a reduced gate-to-drain charge (Q_GD) while maintaining an acceptable breakdown voltage (BV) and specific ON-resistance (R_ONsp). Compared with conventional LDMOS, a better tradeoff between the static figure of merit (FOM_S, FOM_S = BV²/R_ONsp) and the dynamic figure of merit (FOM_D, FOM_D = R_ONsp · Q_GD) is realized. In the ON-state, the p-type polysilicon gate embedded in the drift region induces multiple plane majority-carrier accumulation layers, leading to a decrease in R_ONsp. In the OFF-state, the metal–insulator–semiconductor (MIS) capacitor, which is composed of extended trench gate, gradual trapezoidal oxide, and N-drift. assists in depleting the drift region. Therefore, the doping concentration of drift region can be significantly lifted, and the BV is increased. Besides, the p-n junction capacitor composed of p-type and n-type polysilicon isolates the field coupling between gate and drain, and the gate-to-drain capacitor (C_GD) is thus reduced. Compared with multiple-plane electron accumulation layer LDMOS (MAL LDMOS) and split triple-gate LDMOS (STG-LDMOS), Q_GD and R_ONsp of our proposed PTG LDMOS are shrunk by 34.3% and 54.4%, respectively. In general, the proposed PTG LDMOS achieves a better tradeoff between the static and switching characteristics.