CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array

Pengfei Dai; Na Lu; Anran Gao; Yuelin Wang; Tie Li

doi:10.1109/DTIP.2015.7160980

CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array

Pengfei Dai, Na Lu, Anran Gao, Yuelin Wang, Tie Li

CAS - Shanghai Institute of Microsystem and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a novel method is introduced to fabricate nanoscale silicon oxide islands array. Rectangle islands patterns with edge length less than 100 nm are fabricated by traditional contact lithography and buffered oxide etching process. Precise sacrificial layer etching technique is used to control the size of islands from micro-scale to nanoscale accurately. This fabrication method is CMOS compatible and can realize mass production of nanoscale patterns array in very low cost.

Original language	English
Title of host publication	Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015
Editors	Gerold Schropfer, Francis Pressecq, Marta Rencz, Peter Schneider, Yoshio Mita, Benoit Charlot, Pascal Nouet
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479986255
DOIs	https://doi.org/10.1109/DTIP.2015.7160980
State	Published - 16 Jul 2015
Externally published	Yes
Event	17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 - Montpellier, France Duration: 27 Apr 2015 → 30 Apr 2015

Publication series

Name	Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015

Conference

Conference	17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015
Country/Territory	France
City	Montpellier
Period	27/04/15 → 30/04/15

Keywords

CMOS Compatible
fabrication
island array
low cost
nanoscale

Access to Document

10.1109/DTIP.2015.7160980

Cite this

Dai, P., Lu, N., Gao, A., Wang, Y., & Li, T. (2015). CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array. In G. Schropfer, F. Pressecq, M. Rencz, P. Schneider, Y. Mita, B. Charlot, & P. Nouet (Eds.), Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 Article 7160980 (Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DTIP.2015.7160980

Dai, Pengfei ; Lu, Na ; Gao, Anran et al. / CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array. Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015. editor / Gerold Schropfer ; Francis Pressecq ; Marta Rencz ; Peter Schneider ; Yoshio Mita ; Benoit Charlot ; Pascal Nouet. Institute of Electrical and Electronics Engineers Inc., 2015. (Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015).

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title = "CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array",

abstract = "In this paper, a novel method is introduced to fabricate nanoscale silicon oxide islands array. Rectangle islands patterns with edge length less than 100 nm are fabricated by traditional contact lithography and buffered oxide etching process. Precise sacrificial layer etching technique is used to control the size of islands from micro-scale to nanoscale accurately. This fabrication method is CMOS compatible and can realize mass production of nanoscale patterns array in very low cost.",

keywords = "CMOS Compatible, fabrication, island array, low cost, nanoscale",

author = "Pengfei Dai and Na Lu and Anran Gao and Yuelin Wang and Tie Li",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 ; Conference date: 27-04-2015 Through 30-04-2015",

year = "2015",

month = jul,

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doi = "10.1109/DTIP.2015.7160980",

language = "英语",

series = "Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Gerold Schropfer and Francis Pressecq and Marta Rencz and Peter Schneider and Yoshio Mita and Benoit Charlot and Pascal Nouet",

booktitle = "Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015",

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Dai, P, Lu, N, Gao, A, Wang, Y & Li, T 2015, CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array. in G Schropfer, F Pressecq, M Rencz, P Schneider, Y Mita, B Charlot & P Nouet (eds), Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015., 7160980, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015, Institute of Electrical and Electronics Engineers Inc., 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015, Montpellier, France, 27/04/15. https://doi.org/10.1109/DTIP.2015.7160980

CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array. / Dai, Pengfei; Lu, Na; Gao, Anran et al.
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015. ed. / Gerold Schropfer; Francis Pressecq; Marta Rencz; Peter Schneider; Yoshio Mita; Benoit Charlot; Pascal Nouet. Institute of Electrical and Electronics Engineers Inc., 2015. 7160980 (Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array

AU - Dai, Pengfei

AU - Lu, Na

AU - Gao, Anran

AU - Wang, Yuelin

AU - Li, Tie

PY - 2015/7/16

Y1 - 2015/7/16

N2 - In this paper, a novel method is introduced to fabricate nanoscale silicon oxide islands array. Rectangle islands patterns with edge length less than 100 nm are fabricated by traditional contact lithography and buffered oxide etching process. Precise sacrificial layer etching technique is used to control the size of islands from micro-scale to nanoscale accurately. This fabrication method is CMOS compatible and can realize mass production of nanoscale patterns array in very low cost.

AB - In this paper, a novel method is introduced to fabricate nanoscale silicon oxide islands array. Rectangle islands patterns with edge length less than 100 nm are fabricated by traditional contact lithography and buffered oxide etching process. Precise sacrificial layer etching technique is used to control the size of islands from micro-scale to nanoscale accurately. This fabrication method is CMOS compatible and can realize mass production of nanoscale patterns array in very low cost.

KW - CMOS Compatible

KW - fabrication

KW - island array

KW - low cost

KW - nanoscale

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DO - 10.1109/DTIP.2015.7160980

M3 - 会议稿件

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BT - Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015

A2 - Schropfer, Gerold

A2 - Pressecq, Francis

A2 - Rencz, Marta

A2 - Schneider, Peter

A2 - Mita, Yoshio

A2 - Charlot, Benoit

A2 - Nouet, Pascal

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015

Y2 - 27 April 2015 through 30 April 2015

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Dai P, Lu N, Gao A, Wang Y, Li T. CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array. In Schropfer G, Pressecq F, Rencz M, Schneider P, Mita Y, Charlot B, Nouet P, editors, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7160980. (Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015). doi: 10.1109/DTIP.2015.7160980

CMOS compatible pinpointed fabrication of nanoscale silicon oxide islands array

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Keywords

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