@inproceedings{10fa9b1a07b24335a4eb23ca93964457,
title = "Cache coherence enabled adaptive refresh for volatile STT-RAM",
abstract = "Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead.",
author = "Jianhua Li and Liang Shi and Qing'an Li and Xue, \{Chun Jason\} and Yiran Chen and Yinlong Xu",
year = "2013",
doi = "10.7873/date.2013.258",
language = "英语",
isbn = "9783981537000",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1247--1250",
booktitle = "Proceedings - Design, Automation and Test in Europe, DATE 2013",
address = "美国",
note = "16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conference date: 18-03-2013 Through 22-03-2013",
}