Bus minimization and scheduling of multi-chip systems

Michael Sheliga; Edwin Hsing Mean Sha

Bus minimization and scheduling of multi-chip systems

Michael Sheliga, Edwin Hsing Mean Sha

University of Notre Dame

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.

Original language	English
Pages (from-to)	40-45
Number of pages	6
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
State	Published - 1995
Externally published	Yes
Event	Proceedings of the 5th Great Lakes Symposium on VLSI - Buffalo, NY, USA Duration: 16 Mar 1995 → 18 Mar 1995

Cite this

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title = "Bus minimization and scheduling of multi-chip systems",

abstract = "This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.",

author = "Michael Sheliga and Sha, \{Edwin Hsing Mean\}",

year = "1995",

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AU - Sha, Edwin Hsing Mean

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AB - This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.

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M3 - 会议文章

AN - SCOPUS:0029213242

SN - 1066-1395

SP - 40

EP - 45

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 5th Great Lakes Symposium on VLSI

Y2 - 16 March 1995 through 18 March 1995

ER -

Bus minimization and scheduling of multi-chip systems

Abstract

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