BiCMOS PLL frequency synthesizer for UHF receiver

This paper describes the design of a low power charge pump phase-locked loop(CPPLL) frequency synthesizer circuits which provide local oscillator for mixer in receiver. The receiver working at ISM band from 290 MHz to 470 MHz is implemented in the AMS 0.8 μm BiCMOS process with 12 GHz npn transistor and 650 MHz lateral pnp transistor. The CPPLL circuit uses a digital phase-frequency detector (PFD) which provides a wide frequency acquisition capability. An on-chip charge pump is designed for no dead zone. The LC-tuned negative-resistance voltage controlled oscillator (VCO) has a measured center frequency of 433 MHz and a tuning range 290~520 MHz. A stack mode divider is designed for low power. The total power consumption of CPPLL is 1.4 mA with 5 V supply voltage.