An optimized sigma-delta fractional-N frequency synthesizer for monolithic CMOS UHF RFID reader

Runxi Zhang; Wei He; Chunqi Shi; Zongsheng Lai

An optimized sigma-delta fractional-N frequency synthesizer for monolithic CMOS UHF RFID reader

Runxi Zhang^*, Wei He, Chunqi Shi, Zongsheng Lai

^*Corresponding author for this work

School of Communication and Electronic Engineering

East China Normal University

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

A novel 3rd-order 3-bit single-loop sigma-delta fractional-N frequency synthesizer optimized for monolithic UHF RFID reader is fabricated in 0.18 μm CMOS technology. The phase noise requirements are recapitulated based on the proposed zero-IF architecture and EPCglobal C1G2 and ETSI RFID protocols. The measurement results show that the frequency synthesizer achieves noise suppression for additional zero configuration in noise transfer function of modulator. The measured phase noise is approximately-103 and-132 dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz center frequency while drawing 9.6 mA from 1.8 V power supply.

Original language	English
Pages (from-to)	251-255
Number of pages	5
Journal	Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics
Volume	30
Issue number	2
State	Published - Jun 2010

Keywords

Fractional-N
Frequency synthesizer
Reader
UHF RFID

Cite this

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title = "An optimized sigma-delta fractional-N frequency synthesizer for monolithic CMOS UHF RFID reader",

abstract = "A novel 3rd-order 3-bit single-loop sigma-delta fractional-N frequency synthesizer optimized for monolithic UHF RFID reader is fabricated in 0.18 μm CMOS technology. The phase noise requirements are recapitulated based on the proposed zero-IF architecture and EPCglobal C1G2 and ETSI RFID protocols. The measurement results show that the frequency synthesizer achieves noise suppression for additional zero configuration in noise transfer function of modulator. The measured phase noise is approximately-103 and-132 dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz center frequency while drawing 9.6 mA from 1.8 V power supply.",

keywords = "Fractional-N, Frequency synthesizer, Reader, UHF RFID",

author = "Runxi Zhang and Wei He and Chunqi Shi and Zongsheng Lai",

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T1 - An optimized sigma-delta fractional-N frequency synthesizer for monolithic CMOS UHF RFID reader

AU - Zhang, Runxi

AU - He, Wei

AU - Shi, Chunqi

AU - Lai, Zongsheng

PY - 2010/6

Y1 - 2010/6

N2 - A novel 3rd-order 3-bit single-loop sigma-delta fractional-N frequency synthesizer optimized for monolithic UHF RFID reader is fabricated in 0.18 μm CMOS technology. The phase noise requirements are recapitulated based on the proposed zero-IF architecture and EPCglobal C1G2 and ETSI RFID protocols. The measurement results show that the frequency synthesizer achieves noise suppression for additional zero configuration in noise transfer function of modulator. The measured phase noise is approximately-103 and-132 dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz center frequency while drawing 9.6 mA from 1.8 V power supply.

AB - A novel 3rd-order 3-bit single-loop sigma-delta fractional-N frequency synthesizer optimized for monolithic UHF RFID reader is fabricated in 0.18 μm CMOS technology. The phase noise requirements are recapitulated based on the proposed zero-IF architecture and EPCglobal C1G2 and ETSI RFID protocols. The measurement results show that the frequency synthesizer achieves noise suppression for additional zero configuration in noise transfer function of modulator. The measured phase noise is approximately-103 and-132 dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz center frequency while drawing 9.6 mA from 1.8 V power supply.

KW - Fractional-N

KW - Frequency synthesizer

KW - Reader

KW - UHF RFID

UR - https://www.scopus.com/pages/publications/77954674688

M3 - 文章

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SN - 1000-3819

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EP - 255

JO - Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics

JF - Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics

IS - 2

ER -

An optimized sigma-delta fractional-N frequency synthesizer for monolithic CMOS UHF RFID reader

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Keywords

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