An Optimized ΔΣ modulator in fractional-N frequency synthesizer for UHF RFID Reader

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Abstract

A 3rd-order 3-bit single-loop ΔΣ modulator in fractional-N frequency synthesizer for UHF RFID Reader is optimized in terms of phase noise. Feed forward and feedback path structure is proposed in the ΔΣ modulator. The location of zeros and poles are placed at desired frequency for noise shaping by configuring feed forward and feedback coefficients. A fully integrated ΔΣ fractional-N frequency synthesizer with digital ΔΣ modulator is implemented in 0.18mu;m CMOS technology. The measured phase noise of the proposed ΔΣ fractional-N frequency synthesizer is -76dBc/Hz in-band and -125dBc/Hz at 1MHz offset from 856 MHz carrier and a loop bandwidth of 50 kHz. The rms jitter is 6.74ps and the integrated phase noise is 2.08° from 10kHz to 10MHz frequency offset.

Original languageEnglish
Title of host publication2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010
Pages1468-1471
Number of pages4
DOIs
StatePublished - 2010
Event2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010 - Chengdu, China
Duration: 8 May 201011 May 2010

Publication series

Name2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010

Conference

Conference2010 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2010
Country/TerritoryChina
CityChengdu
Period8/05/1011/05/10

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