An optimized ΔΣ fractional-N frequency synthesizer for CMOS UHF RFID reader

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2 Scopus citations

Abstract

A novel 3-bit 3rd-order ΔΣ fractional-N frequency synthesizer specialized for monolithic UHF band radio frequency identification reader is implemented in 0.18μm CMOS technology. The phase noise requirements are recapitulated for the zero-IF transceiver architecture and EPC global C1G2 and ETSI multi-protocol operation. The measurement results show that the synthesizer phase noise at 200 kHz offset is suppressed by the additional zero configuration in delta-sigma modulator (DSM)'s noise transfer function with acceptable in-band noise penalty. The measured phase noise is -102 and -126.5dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz operation frequency while drawing 9.6 mA from 1.8 V power supply.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages545-548
Number of pages4
DOIs
StatePublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
Duration: 20 Oct 200923 Oct 2009

Publication series

NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Conference

Conference2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/TerritoryChina
CityChangsha
Period20/10/0923/10/09

Keywords

  • CMOS
  • Delta-sigma(ΔΣ)
  • Fractional-N synthesizer
  • Ultra-high-frequency radio-frequency identification (UHF RFID)

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