An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving −251.9 dB FOM_Jitter-N

This paper presents a reference double-sampling phase-locked loop (RDSPLL) that integrates frequency multiplication and octa-phase clock generation into a single system, significantly reducing power consumption. A differential ring oscillator (DRO) is employed to generate octa-phase clocks with high phase accuracy. The reference double-sampling technique extends the loop bandwidth, effectively suppressing phase noise from the ring oscillator and thereby reducing jitter. To achieve accurate and efficient phase error detection, we proposed a novel offset-compensated hybrid phase detector (OCH-PD), featuring an offset calibration and a comparator-ADC hybrid quantizer. The offset calibration utilizes the CDAC to dynamically compensate for the mismatch in double-sampling, improving jitter and spur performance. The hybrid quantizer supports dynamic mode switching based on different locking states: during the coarse frequency locking phase, it operates in the ADC mode to accelerate the locking process; once a stable lock is achieved, it switches to the comparator mode to enable low-power, high-speed quantization. Fabricated in a 65-nm CMOS process, the prototype achieves 674 fs RMS jitter at 2.4 GHz while consuming only 3.43 mW, resulting in a FOM_Jitter-N of -251.9 dB. With offset calibration, the reference spur at 100 MHz is suppressed from -56 dBc to -80 dBc, and the jitter is reduced from 1.42 ps to 674 fs. The locking time improves from 10.5 μs to 1.6 μs using the hybrid quantizer. The eight-phase accuracy remains better than 1° over the frequency range of 2-2.8 GHz.