An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar

Leibin Ni; Yuhao Wang; Hao Yu; Wei Yang; Chuliang Weng; Junfeng Zhao

doi:10.1109/ASPDAC.2016.7428024

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar

Leibin Ni
, Yuhao Wang
, Hao Yu
, Wei Yang
, Chuliang Weng
, Junfeng Zhao

Nanyang Technological University
Huawei Technologies Co., Ltd.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

45 Scopus citations

Abstract

Emerging resistive random-access memory (RRAM) can provide non-volatile memory storage but also intrinsic logic for matrix-vector multiplication, which is ideal for low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM-based computing device is mainly assumed on a multi-level analog computing, whose result is sensitive to process non-uniformity as well as additional AD-conversion and I/O overhead. This paper explores the data analytics accelerator on binary RRAM-crossbar. Accordingly, one distributed in-memory computing architecture is proposed with design of according component and control protocol. Both memory array and logic accelerator can be implemented by RRAM-crossbar purely in binary, where logic-memory pairs can be distributed with protocol of control bus. Based on numerical results for fingerprint matching that is mapped on the proposed RRAM-crossbar, the proposed architecture has shown 2.86x faster speed, 154x better energy efficiency, and 100x smaller area when compared to the same design by CMOS-based ASIC.

Original language	English
Title of host publication	2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	280-285
Number of pages	6
ISBN (Electronic)	9781467395694
DOIs	https://doi.org/10.1109/ASPDAC.2016.7428024
State	Published - 7 Mar 2016
Externally published	Yes
Event	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao Duration: 25 Jan 2016 → 28 Jan 2016

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	25-28-January-2016

Conference

Conference	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Country/Territory	Macao
City	Macao
Period	25/01/16 → 28/01/16

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/ASPDAC.2016.7428024

Cite this

Ni, L., Wang, Y., Yu, H., Yang, W., Weng, C., & Zhao, J. (2016). An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 280-285). Article 7428024 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7428024

Ni, Leibin ; Wang, Yuhao ; Yu, Hao et al. / An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 280-285 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

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title = "An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar",

abstract = "Emerging resistive random-access memory (RRAM) can provide non-volatile memory storage but also intrinsic logic for matrix-vector multiplication, which is ideal for low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM-based computing device is mainly assumed on a multi-level analog computing, whose result is sensitive to process non-uniformity as well as additional AD-conversion and I/O overhead. This paper explores the data analytics accelerator on binary RRAM-crossbar. Accordingly, one distributed in-memory computing architecture is proposed with design of according component and control protocol. Both memory array and logic accelerator can be implemented by RRAM-crossbar purely in binary, where logic-memory pairs can be distributed with protocol of control bus. Based on numerical results for fingerprint matching that is mapped on the proposed RRAM-crossbar, the proposed architecture has shown 2.86x faster speed, 154x better energy efficiency, and 100x smaller area when compared to the same design by CMOS-based ASIC.",

author = "Leibin Ni and Yuhao Wang and Hao Yu and Wei Yang and Chuliang Weng and Junfeng Zhao",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 ; Conference date: 25-01-2016 Through 28-01-2016",

year = "2016",

month = mar,

day = "7",

doi = "10.1109/ASPDAC.2016.7428024",

language = "英语",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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Ni, L, Wang, Y, Yu, H, Yang, W, Weng, C & Zhao, J 2016, An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016., 7428024, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 25-28-January-2016, Institute of Electrical and Electronics Engineers Inc., pp. 280-285, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, 25/01/16. https://doi.org/10.1109/ASPDAC.2016.7428024

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. / Ni, Leibin; Wang, Yuhao; Yu, Hao et al.
2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 280-285 7428024 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar

AU - Ni, Leibin

AU - Wang, Yuhao

AU - Yu, Hao

AU - Yang, Wei

AU - Weng, Chuliang

AU - Zhao, Junfeng

PY - 2016/3/7

Y1 - 2016/3/7

N2 - Emerging resistive random-access memory (RRAM) can provide non-volatile memory storage but also intrinsic logic for matrix-vector multiplication, which is ideal for low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM-based computing device is mainly assumed on a multi-level analog computing, whose result is sensitive to process non-uniformity as well as additional AD-conversion and I/O overhead. This paper explores the data analytics accelerator on binary RRAM-crossbar. Accordingly, one distributed in-memory computing architecture is proposed with design of according component and control protocol. Both memory array and logic accelerator can be implemented by RRAM-crossbar purely in binary, where logic-memory pairs can be distributed with protocol of control bus. Based on numerical results for fingerprint matching that is mapped on the proposed RRAM-crossbar, the proposed architecture has shown 2.86x faster speed, 154x better energy efficiency, and 100x smaller area when compared to the same design by CMOS-based ASIC.

AB - Emerging resistive random-access memory (RRAM) can provide non-volatile memory storage but also intrinsic logic for matrix-vector multiplication, which is ideal for low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM-based computing device is mainly assumed on a multi-level analog computing, whose result is sensitive to process non-uniformity as well as additional AD-conversion and I/O overhead. This paper explores the data analytics accelerator on binary RRAM-crossbar. Accordingly, one distributed in-memory computing architecture is proposed with design of according component and control protocol. Both memory array and logic accelerator can be implemented by RRAM-crossbar purely in binary, where logic-memory pairs can be distributed with protocol of control bus. Based on numerical results for fingerprint matching that is mapped on the proposed RRAM-crossbar, the proposed architecture has shown 2.86x faster speed, 154x better energy efficiency, and 100x smaller area when compared to the same design by CMOS-based ASIC.

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Y2 - 25 January 2016 through 28 January 2016

ER -

Ni L, Wang Y, Yu H, Yang W, Weng C, Zhao J. An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 280-285. 7428024. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2016.7428024

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar

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