An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process

This paper presents a high speed CMOS hybrid comparator with reduced delay time and improved energy efficiency. The proposed hybrid comparator includes two stages with three stacked transistors which are suitable for low-voltage operation. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, while enhancing the positive feedback to reduce the discharging time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain the transconductance, thus reducing the latching time with negligible static power, while needing no additional clock signal. Therefore, the delay time and energy per conversion are both significantly reduced in the proposed hybrid comparator. Measurement results in 40-nm CMOS process show that the proposed hybrid comparator operates up to 6 GHz with 61.08-ps delay time. The power consumption is 345.9 μ W at 1.1-V supply, while the occupied die area is 64.5 μ m² (7.5 μ m × 8.6 μ m).