An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks

Bicheng Liu; Shouzhen Gu; Mingsong Chen; Wang Kang; Jingtong Hu; Qingfeng Zhuge; Edwin H.M. Sha

doi:10.1109/ISPA/IUCC.2017.00061

An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks

Bicheng Liu
, Shouzhen Gu
, Mingsong Chen
, Wang Kang
, Jingtong Hu
, Qingfeng Zhuge
, Edwin H.M. Sha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

As a promising architectural paradigm for applications which demand high I/O bandwidth, Processing-in-Memory (PIM) computing techniques have been adopted in designing Convolutional Neural Networks (CNNs). However, due to the notorious memory wall problem, PIM based on existing device memory still cannot deal with complex CNN applications under the constraints of memory bandwidth and processing latency. To mitigate this problem, this paper proposes an efficient PIM archi-tecture based on skyrmion and domain-wall racetrack memories, which can further exploit the potential of PIM architectures in terms of processing latency and energy efficiency. By adopting full adders and multipliers developed using skyrmion and domain-wall nanowires, our proposed PIM architecture can accommodate complex CNNs at different scales. Experimental results show that comparing with both traditional and state-of-The-Art PIM architectures, our proposed PIM architecture can improve the processing latency and energy efficiency of CNNs drastically.

Original language	English
Title of host publication	Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
Editors	Gregorio Martinez, Richard Hill, Geoffrey Fox, Peter Mueller, Guojun Wang
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	383-390
Number of pages	8
ISBN (Electronic)	9781538637906
DOIs	https://doi.org/10.1109/ISPA/IUCC.2017.00061
State	Published - 25 May 2018
Event	15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 - Guangzhou, China Duration: 12 Dec 2017 → 15 Dec 2017

Publication series

Name	Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017

Conference

Conference	15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017
Country/Territory	China
City	Guangzhou
Period	12/12/17 → 15/12/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Convolutional Neural Networks
Domain Wall
Processing In Memory
Racetrack Memory
Skyrmion

Access to Document

10.1109/ISPA/IUCC.2017.00061

Cite this

Liu, B., Gu, S., Chen, M., Kang, W., Hu, J., Zhuge, Q., & Sha, E. H. M. (2018). An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks. In G. Martinez, R. Hill, G. Fox, P. Mueller, & G. Wang (Eds.), Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 (pp. 383-390). (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISPA/IUCC.2017.00061

Liu, Bicheng ; Gu, Shouzhen ; Chen, Mingsong et al. / An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks. Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. editor / Gregorio Martinez ; Richard Hill ; Geoffrey Fox ; Peter Mueller ; Guojun Wang. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 383-390 (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017).

@inproceedings{13c41639511d4583ae84ee67ca4deca0,

title = "An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks",

abstract = "As a promising architectural paradigm for applications which demand high I/O bandwidth, Processing-in-Memory (PIM) computing techniques have been adopted in designing Convolutional Neural Networks (CNNs). However, due to the notorious memory wall problem, PIM based on existing device memory still cannot deal with complex CNN applications under the constraints of memory bandwidth and processing latency. To mitigate this problem, this paper proposes an efficient PIM archi-tecture based on skyrmion and domain-wall racetrack memories, which can further exploit the potential of PIM architectures in terms of processing latency and energy efficiency. By adopting full adders and multipliers developed using skyrmion and domain-wall nanowires, our proposed PIM architecture can accommodate complex CNNs at different scales. Experimental results show that comparing with both traditional and state-of-The-Art PIM architectures, our proposed PIM architecture can improve the processing latency and energy efficiency of CNNs drastically.",

keywords = "Convolutional Neural Networks, Domain Wall, Processing In Memory, Racetrack Memory, Skyrmion",

author = "Bicheng Liu and Shouzhen Gu and Mingsong Chen and Wang Kang and Jingtong Hu and Qingfeng Zhuge and Sha, \{Edwin H.M.\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017 ; Conference date: 12-12-2017 Through 15-12-2017",

year = "2018",

month = may,

day = "25",

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language = "英语",

series = "Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "383--390",

editor = "Gregorio Martinez and Richard Hill and Geoffrey Fox and Peter Mueller and Guojun Wang",

booktitle = "Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017",

address = "美国",

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Liu, B, Gu, S , Chen, M, Kang, W, Hu, J, Zhuge, Q & Sha, EHM 2018, An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks. in G Martinez, R Hill, G Fox, P Mueller & G Wang (eds), Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 383-390, 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017, Guangzhou, China, 12/12/17. https://doi.org/10.1109/ISPA/IUCC.2017.00061

An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks. / Liu, Bicheng; Gu, Shouzhen ; Chen, Mingsong et al.
Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. ed. / Gregorio Martinez; Richard Hill; Geoffrey Fox; Peter Mueller; Guojun Wang. Institute of Electrical and Electronics Engineers Inc., 2018. p. 383-390 (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks

AU - Liu, Bicheng

AU - Gu, Shouzhen

AU - Chen, Mingsong

AU - Kang, Wang

AU - Hu, Jingtong

AU - Zhuge, Qingfeng

AU - Sha, Edwin H.M.

PY - 2018/5/25

Y1 - 2018/5/25

N2 - As a promising architectural paradigm for applications which demand high I/O bandwidth, Processing-in-Memory (PIM) computing techniques have been adopted in designing Convolutional Neural Networks (CNNs). However, due to the notorious memory wall problem, PIM based on existing device memory still cannot deal with complex CNN applications under the constraints of memory bandwidth and processing latency. To mitigate this problem, this paper proposes an efficient PIM archi-tecture based on skyrmion and domain-wall racetrack memories, which can further exploit the potential of PIM architectures in terms of processing latency and energy efficiency. By adopting full adders and multipliers developed using skyrmion and domain-wall nanowires, our proposed PIM architecture can accommodate complex CNNs at different scales. Experimental results show that comparing with both traditional and state-of-The-Art PIM architectures, our proposed PIM architecture can improve the processing latency and energy efficiency of CNNs drastically.

AB - As a promising architectural paradigm for applications which demand high I/O bandwidth, Processing-in-Memory (PIM) computing techniques have been adopted in designing Convolutional Neural Networks (CNNs). However, due to the notorious memory wall problem, PIM based on existing device memory still cannot deal with complex CNN applications under the constraints of memory bandwidth and processing latency. To mitigate this problem, this paper proposes an efficient PIM archi-tecture based on skyrmion and domain-wall racetrack memories, which can further exploit the potential of PIM architectures in terms of processing latency and energy efficiency. By adopting full adders and multipliers developed using skyrmion and domain-wall nanowires, our proposed PIM architecture can accommodate complex CNNs at different scales. Experimental results show that comparing with both traditional and state-of-The-Art PIM architectures, our proposed PIM architecture can improve the processing latency and energy efficiency of CNNs drastically.

KW - Convolutional Neural Networks

KW - Domain Wall

KW - Processing In Memory

KW - Racetrack Memory

KW - Skyrmion

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DO - 10.1109/ISPA/IUCC.2017.00061

M3 - 会议稿件

AN - SCOPUS:85048370858

T3 - Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017

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BT - Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017

A2 - Martinez, Gregorio

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A2 - Fox, Geoffrey

A2 - Mueller, Peter

A2 - Wang, Guojun

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017

Y2 - 12 December 2017 through 15 December 2017

ER -

Liu B, Gu S , Chen M, Kang W, Hu J, Zhuge Q et al. An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks. In Martinez G, Hill R, Fox G, Mueller P, Wang G, editors, Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 383-390. (Proceedings - 15th IEEE International Symposium on Parallel and Distributed Processing with Applications and 16th IEEE International Conference on Ubiquitous Computing and Communications, ISPA/IUCC 2017). doi: 10.1109/ISPA/IUCC.2017.00061

An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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