TY - GEN
T1 - An efficient cache management scheme for capacitor equipped solid state drives
AU - Gao, Congming
AU - Shi, Liang
AU - Di, Yejia
AU - Li, Qiao
AU - Xue, Chun Jason
AU - Sha, Edwin H.M.
N1 - Publisher Copyright:
© 2018 Association for Computing Machinery.
PY - 2018/5/30
Y1 - 2018/5/30
N2 - Within SSDs, random access memory (RAM) has been adopted as cache inside controller for achieving better performance. However, due to the volatility characteristic of RAM, data loss may happen when sudden power interrupts. To solve this issue, capacitor has been equipped inside emerging SSDs as interim supplier. However, the aging issue of capacitor will result in capacitance decreases over time. Once the remaining capacitance is not able to write all dirty pages in the cache back to flash memory, data loss may happen. In order to solve the above issue, an efficient cache management scheme for capacitor equipped SSDs is proposed in this work. The basic idea of the scheme is to bound the number of dirty pages in cache within the capability of the capacitor. Simulation results show that the proposed scheme achieves encourage improvement on lifetime and performance while power interruption induced data loss is avoided.
AB - Within SSDs, random access memory (RAM) has been adopted as cache inside controller for achieving better performance. However, due to the volatility characteristic of RAM, data loss may happen when sudden power interrupts. To solve this issue, capacitor has been equipped inside emerging SSDs as interim supplier. However, the aging issue of capacitor will result in capacitance decreases over time. Once the remaining capacitance is not able to write all dirty pages in the cache back to flash memory, data loss may happen. In order to solve the above issue, an efficient cache management scheme for capacitor equipped SSDs is proposed in this work. The basic idea of the scheme is to bound the number of dirty pages in cache within the capability of the capacitor. Simulation results show that the proposed scheme achieves encourage improvement on lifetime and performance while power interruption induced data loss is avoided.
UR - https://www.scopus.com/pages/publications/85049448278
U2 - 10.1145/3194554.3194639
DO - 10.1145/3194554.3194639
M3 - 会议稿件
AN - SCOPUS:85049448278
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 463
EP - 466
BT - GLSVLSI 2018 - Proceedings of the 2018 Great Lakes Symposium on VLSI
PB - Association for Computing Machinery
T2 - 28th Great Lakes Symposium on VLSI, GLSVLSI 2018
Y2 - 23 May 2018 through 25 May 2018
ER -