An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology

  • Yulang Feng
  • , Qingjun Fan
  • , Hao Deng
  • , Jeffrey Chen
  • , Runxi Zhang
  • , Phaneendra Bikkina
  • , Jinghong Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

This paper presents an automatic comparator offset calibration scheme for designing high-speed flash analog-to-digital data converters (ADCs). It leverages the threshold voltage control capability via back-gate in FDSOI CMOS technology and thus does not require extra transistor pairs or capacitive loads, avoiding comparator speed degradation. An automatic calibration approach employing a successive approximation algorithm (SAA) is also developed. The comparator along with the calibration circuit are designed in a 28-nm FDSOI CMOS process. Simulation results show that the design achieves a resolution of 1.84 mV and a calibration range of ±58 mV with a power consumption of 440 μW under a 1V power supply.

Original languageEnglish
Title of host publication2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728134277
DOIs
StatePublished - Feb 2020
Event11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica
Duration: 25 Feb 202028 Feb 2020

Publication series

Name2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

Conference

Conference11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
Country/TerritoryCosta Rica
CitySan Jose
Period25/02/2028/02/20

Keywords

  • FDSOI
  • High-speed comparator
  • flash ADC
  • offset calibration

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