An Analytical Compact Model for Multi-time Programmable Memory Cells

Single-poly multi-time programmable (MTP) memory cell demonstrates promising prospects in embedded nonvolatile memory technologies. In this paper, a novel analytic compact model is proposed for erasing/programming operations in MTP memory cells. The model incorporates the effects of ramp voltage slew rate on memory cells and, based on the capacitive coupling coefficient model, constructs a computational framework to derive closed-form analytical solutions. Compared to the prior approaches, this methodology achieves computational simplicity without iterative calculation. Furthermore, model predictions demonstrate good agreement with experimental data (error < 2.16%). The proposed framework enables rapid performance evaluation of memory cells, delivering a guiding framework for cooptimizing memory cell architecture and peripheral circuit design.