@inproceedings{c4234de3506a4e95b89edc0322ccd5c8,
title = "A Type-I Reference Sampling pll with Locking Region Tracking Achieving - 261.8 dB FoMjitter, N and 7\% Jitter Variation Over PVT",
abstract = "This work presents a type-I differential double-edge reference-sampling ring-oscillator based phase-locked loop (DDERSPLL) utilizing locking region tracking (LRT) to achieve low jitter over process, voltage and temperature (PVT) variations. The differential double-edge sampling technique is used to widen loop bandwidth (BWloop) and suppress the phase noise of the ring oscillator. The LRT is introduced to maintain the sampling points in the high-gain region to eliminate phase detection gain (KPD) variation and maintain high KPD and wide BWLoop over PVT variations. The prototype PLL implemented in 65-nm CMOS achieves 426 fs jitterRMS and consumes only 1.42 mW, corresponding to a - 245.8 dB FoMjitter and a - 261.8 dB FoMjitter, N. Over a temperature span of -45°C to 105° C and supply voltage variations of ± 15\% (i.e., 0.85 V to 1.15 V), the measured jitterRMS deviation remains within 7\%.",
keywords = "Loop Bandwidth, Phase Detection Gain, PVT Robustness, Reference Sampling, Type-I Phase-Locked Loop",
author = "Weijia Zeng and Kaiyun Cao and Sirou Li and Rongjin Xu and Liangjian Lyu and Xing Wu and Shi, \{C. J.Richard\}",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 ; Conference date: 08-09-2025 Through 11-09-2025",
year = "2025",
doi = "10.1109/ESSERC66193.2025.11214014",
language = "英语",
series = "European Solid-State Circuits Conference",
publisher = "IEEE Computer Society",
pages = "153--156",
booktitle = "Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025",
address = "美国",
}