A symbolic approach for detecting conflicts in Verilog's non blocking assignments

Peng Liu; Huibiao Zhu; Naiyong Jin

doi:10.1109/ICSICT.2012.6467951

A symbolic approach for detecting conflicts in Verilog's non blocking assignments

Peng Liu^*
, Huibiao Zhu
, Naiyong Jin

^*Corresponding author for this work

Software Engineering Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In Verilog programs, multiple non blocking assignments (NBA) to the same signal in an identical always structure may introduce conflicts and nondeterministic behaviors. It is a severe design flaw. In this paper, we propose a control flow graph based symbolic approach for detecting conflicts caused by non blocking assignments. This approach applies the static analysis method on the parallel nature of Verilog programs, and adopts the Multi-valued Decision Diagram (MDD) to symbolically encode the reachability conditions with flexibility and efficiency. Our static analysis approach shows valid results from our tests.

Original language	English
Title of host publication	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs	https://doi.org/10.1109/ICSICT.2012.6467951
State	Published - 2012
Event	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China Duration: 29 Oct 2012 → 1 Nov 2012

Publication series

Name	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Country/Territory	China
City	Xi'an
Period	29/10/12 → 1/11/12

Keywords

Conflict Detection
Static Verification
Symbolic Approach

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10.1109/ICSICT.2012.6467951

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Liu, P., Zhu, H., & Jin, N. (2012). A symbolic approach for detecting conflicts in Verilog's non blocking assignments. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings Article 6467951 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2012.6467951

@inproceedings{986b87514dd543a49b83fd4970a204fc,

title = "A symbolic approach for detecting conflicts in Verilog's non blocking assignments",

abstract = "In Verilog programs, multiple non blocking assignments (NBA) to the same signal in an identical always structure may introduce conflicts and nondeterministic behaviors. It is a severe design flaw. In this paper, we propose a control flow graph based symbolic approach for detecting conflicts caused by non blocking assignments. This approach applies the static analysis method on the parallel nature of Verilog programs, and adopts the Multi-valued Decision Diagram (MDD) to symbolically encode the reachability conditions with flexibility and efficiency. Our static analysis approach shows valid results from our tests.",

keywords = "Conflict Detection, Static Verification, Symbolic Approach",

author = "Peng Liu and Huibiao Zhu and Naiyong Jin",

year = "2012",

doi = "10.1109/ICSICT.2012.6467951",

language = "英语",

isbn = "9781467324724",

series = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

booktitle = "ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

note = "2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 ; Conference date: 29-10-2012 Through 01-11-2012",

}

Liu, P, Zhu, H & Jin, N 2012, A symbolic approach for detecting conflicts in Verilog's non blocking assignments. in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 6467951, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012, Xi'an, China, 29/10/12. https://doi.org/10.1109/ICSICT.2012.6467951

A symbolic approach for detecting conflicts in Verilog's non blocking assignments. / Liu, Peng; Zhu, Huibiao; Jin, Naiyong.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467951 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A symbolic approach for detecting conflicts in Verilog's non blocking assignments

AU - Liu, Peng

AU - Zhu, Huibiao

AU - Jin, Naiyong

PY - 2012

Y1 - 2012

N2 - In Verilog programs, multiple non blocking assignments (NBA) to the same signal in an identical always structure may introduce conflicts and nondeterministic behaviors. It is a severe design flaw. In this paper, we propose a control flow graph based symbolic approach for detecting conflicts caused by non blocking assignments. This approach applies the static analysis method on the parallel nature of Verilog programs, and adopts the Multi-valued Decision Diagram (MDD) to symbolically encode the reachability conditions with flexibility and efficiency. Our static analysis approach shows valid results from our tests.

AB - In Verilog programs, multiple non blocking assignments (NBA) to the same signal in an identical always structure may introduce conflicts and nondeterministic behaviors. It is a severe design flaw. In this paper, we propose a control flow graph based symbolic approach for detecting conflicts caused by non blocking assignments. This approach applies the static analysis method on the parallel nature of Verilog programs, and adopts the Multi-valued Decision Diagram (MDD) to symbolically encode the reachability conditions with flexibility and efficiency. Our static analysis approach shows valid results from our tests.

KW - Conflict Detection

KW - Static Verification

KW - Symbolic Approach

UR - https://www.scopus.com/pages/publications/84874866622

U2 - 10.1109/ICSICT.2012.6467951

DO - 10.1109/ICSICT.2012.6467951

M3 - 会议稿件

AN - SCOPUS:84874866622

SN - 9781467324724

T3 - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

BT - ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

T2 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012

Y2 - 29 October 2012 through 1 November 2012

ER -

Liu P, Zhu H, Jin N. A symbolic approach for detecting conflicts in Verilog's non blocking assignments. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467951. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2012.6467951

A symbolic approach for detecting conflicts in Verilog's non blocking assignments

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