A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces

Qingzhen Wang, Wenxian Gu, Hengchang Bi, Liangjian Lyu, Deli Qiao, Xing Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Brain science research requires high-density neural interfaces, where data transmission is challenging in limited power budget. Compressed sensing is a promising approach to reduce data rate of the spike signal, yet the quality of the reconstructed signal greatly depends on the selection of sensing matrix. This paper proposes a spike-sorting-assisted compressed sensing method that exploits using different sensing matrices according to the cluster classes of spikes. The simulated classification accuracy of the proposed method shows a maximum improvement of 20%, i.e., from 70% to 90%. The average classification accuracy achieves 96.26% and 93.34% at a compression ratio of 8 and 16, respectively. Implemented in a 65 nm CMOS process, the proposed processor occupies a core area of 0.073 mm2. The simulated power consumption is 0.931 μW while powered by 0.9 V supply and operating at 24 kHz.

Original languageEnglish
Title of host publicationProceedings of 2023 IEEE 15th International Conference on ASIC, ASICON 2023
EditorsFan Ye, Ting-Ao Tang
PublisherIEEE Computer Society
ISBN (Electronic)9798350312980
DOIs
StatePublished - 2023
Event15th IEEE International Conference on ASIC, ASICON 2023 - Nanjing, China
Duration: 24 Oct 202327 Oct 2023

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference15th IEEE International Conference on ASIC, ASICON 2023
Country/TerritoryChina
CityNanjing
Period24/10/2327/10/23

Keywords

  • compressed sensing
  • digital integrated circuits
  • neural recording
  • spike sorting

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