A robust and fast OPC approach for metal interconnects of 0.13 um logic devices

Insufficient metal overlaps over contacts and/or vias impact serious yield loss especially in the borderless-contact-style random logic devices. Vias which are not fully covered by interconnects cause not only the functional error due to the high via resistance but also the reliability problem such as electromigration. It is not sufficient to compensate only optical proximity effects such as line-end shortening and corner rounding for the overlap margin. Since mis-alignment between interconnects and over/underlying features is not negligible even using an advanced alignment system of step & scanner. Therefore, the need for aggressive OPC is increased to cope with the proximity effect and overlay error in metal interconnects. The proposed OPC approach gives a robust metal overlap with fast runtime and allowable data complexity by selective correction for the improperly overlapped contacts and vias. Experimental results for the test design (2 million gates) show that the correction time of the metall interconnects takes 11 hours at HP5600 system by applying the proposed correction algorithm.