@inproceedings{213ede1997fb4217ac023db763254a65,
title = "A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N",
abstract = "A reference double-sampling phase-locked-loop-based (RDSPLL-based) multi-phase clock generator (MPCG) for DDR PHY is presented. The reference double-sampling architecture is utilized to achieve low phase noise. A CDAC-embedded voltage offset calibration is proposed to reduce jitter and reference spur, and a CMP-ADC hybrid phase detector is adopted to accelerate the locking process. Fabricated in 65nm, the proposed MPCG achieves better than 1° phase accuracy with a 100MHz reference clock. The reference spur is reduced from -56dBc to -80dBc and the locking time is reduced from 10.5us to 1.6us. The measured RMS jitter is 674fs at 2.4GHz with 3.43mW, yielding the FOMJitter-N of -251.9dB.",
keywords = "multi-phase clock generator (MPCG), phase error, reference double-sampling PLL (RDSPLL), ring oscillator",
author = "Sirou Li and Weijia Zeng and Kaiyun Cao and Liangjian Lyu and Shi, \{C. J.Richard\}",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",
year = "2025",
doi = "10.1109/ISCAS56072.2025.11043253",
language = "英语",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",
address = "美国",
}