A quadrature frequency synthesizer with 118.7-fs jitter, <-64 dBC spurs and >27.94% locking range for multiband 5G MMW applications

Runxi Zhang, Hui Yang, Zitong Zhang, Chunqi Shi, Qingjun Fan, Jinghong Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents a quadrature frequency synthesizer (QFS) utilizing a switched-coupled slotted inductor (SCSI)-based voltage-controlled oscillator (VCO) to simultaneously improve the reference spurs and out-of-band phase noise while achieving a wide frequency tuning range for multiband 5G mm-Wave (mmW) applications. The QFS is implemented in a 55 nm CMOS process, achieving a reference spurs of -64 to -72 dBc, an in-band phase noise of -81.7 to -87 dBc/Hz at 100 kHz offset and an out-of-band phase noise of -119.1 to -125.4 dBc/Hz at 10 MHz offset, respectively, over the entire 19.89 to 26.35 GHz frequency locking range. The RMS jitter for a 19.89 GHz carrier is 118.7 fs, corresponding to a jitter FOM of -238.47 dB. The chip occupies a die area of 1.31×2.13 mm2 including the testing pads and dissipates 101 mW of power.

Original languageEnglish
Title of host publication2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728133201
StatePublished - 2020
Event52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
Duration: 10 Oct 202021 Oct 2020

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2020-October
ISSN (Print)0271-4310

Conference

Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
CityVirtual, Online
Period10/10/2021/10/20

Keywords

  • Mm-Wave (mmW)
  • PLL
  • Switched-coupled slotted inductor (SCSI)
  • Voltage-controlled oscillator (VCO)

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