A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells

Zhiyuan Song; Aibin Yan; Jie Cui; Zhili Chen; Xuejun Li; Xiaoqing Wen; Chaoping Lai; Zhengfeng Huang; Huaguo Liang

doi:10.1109/ITC-Asia.2019.00037

A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells

Zhiyuan Song
, Aibin Yan
, Jie Cui
, Zhili Chen
, Xuejun Li
, Xiaoqing Wen
, Chaoping Lai
, Zhengfeng Huang
, Huaguo Liang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

35 Scopus citations

Abstract

Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81% for the proposed latch compared with the only existing SETU hardened latch.

Original language	English
Title of host publication	Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	139-144
Number of pages	6
ISBN (Electronic)	9781728147185
DOIs	https://doi.org/10.1109/ITC-Asia.2019.00037
State	Published - Sep 2019
Externally published	Yes
Event	3rd IEEE International Test Conference in Asia, ITC-Asia 2019 - Tokyo, Japan Duration: 3 Sep 2019 → 5 Sep 2019

Publication series

Name	Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019

Conference

Conference	3rd IEEE International Test Conference in Asia, ITC-Asia 2019
Country/Territory	Japan
City	Tokyo
Period	3/09/19 → 5/09/19

Keywords

C element
Hardened latch
Single node upset
Triple node upset

Access to Document

10.1109/ITC-Asia.2019.00037

Cite this

Song, Z., Yan, A., Cui, J., Chen, Z., Li, X., Wen, X., Lai, C., Huang, Z., & Liang, H. (2019). A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells. In Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019 (pp. 139-144). Article 8872050 (Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-Asia.2019.00037

Song, Zhiyuan ; Yan, Aibin ; Cui, Jie et al. / A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells. Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 139-144 (Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019).

@inproceedings{542fe26442eb48dabaf70c2d177dd8c2,

title = "A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells",

abstract = "Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81\% for the proposed latch compared with the only existing SETU hardened latch.",

keywords = "C element, Hardened latch, Single node upset, Triple node upset",

author = "Zhiyuan Song and Aibin Yan and Jie Cui and Zhili Chen and Xuejun Li and Xiaoqing Wen and Chaoping Lai and Zhengfeng Huang and Huaguo Liang",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 3rd IEEE International Test Conference in Asia, ITC-Asia 2019 ; Conference date: 03-09-2019 Through 05-09-2019",

year = "2019",

month = sep,

doi = "10.1109/ITC-Asia.2019.00037",

language = "英语",

series = "Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Song, Z, Yan, A, Cui, J, Chen, Z, Li, X, Wen, X, Lai, C, Huang, Z & Liang, H 2019, A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells. in Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019., 8872050, Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019, Institute of Electrical and Electronics Engineers Inc., pp. 139-144, 3rd IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, 3/09/19. https://doi.org/10.1109/ITC-Asia.2019.00037

A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells. / Song, Zhiyuan; Yan, Aibin; Cui, Jie et al.
Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 139-144 8872050 (Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Song, Zhiyuan

AU - Yan, Aibin

AU - Cui, Jie

AU - Chen, Zhili

AU - Li, Xuejun

AU - Wen, Xiaoqing

AU - Lai, Chaoping

AU - Huang, Zhengfeng

AU - Liang, Huaguo

PY - 2019/9

Y1 - 2019/9

N2 - Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81% for the proposed latch compared with the only existing SETU hardened latch.

AB - Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81% for the proposed latch compared with the only existing SETU hardened latch.

KW - C element

KW - Hardened latch

KW - Single node upset

KW - Triple node upset

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ER -

Song Z, Yan A, Cui J, Chen Z, Li X, Wen X et al. A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells. In Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 139-144. 8872050. (Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019). doi: 10.1109/ITC-Asia.2019.00037

A novel triple-node-upset-tolerant CMOS latch design using single-node-upset-resilient cells

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