A Novel Multiplexer-Based Low-Power Full Adder

Yingtao Jiang; Abdulkarim Al-Sheraidah; Yuke Wang; Edwin Sha; Jin Gyun Chung

doi:10.1109/TCSII.2004.831429

A Novel Multiplexer-Based Low-Power Full Adder

Yingtao Jiang
, Abdulkarim Al-Sheraidah
, Yuke Wang
, Edwin Sha
, Jin Gyun Chung

Research output: Contribution to journal › Article › peer-review

173 Scopus citations

Abstract

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Original language	English
Pages (from-to)	345-348
Number of pages	4
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	51
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2004.831429
State	Published - Jul 2004
Externally published	Yes

Keywords

Full adder
low power
multiplexer
very large-scale integrated (VLSI) circuit

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10.1109/TCSII.2004.831429

Cite this

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title = "A Novel Multiplexer-Based Low-Power Full Adder",

abstract = "The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26\% in power savings over conventional 28-transistor CMOS adder and it consumes 23\% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64\% faster.",

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author = "Yingtao Jiang and Abdulkarim Al-Sheraidah and Yuke Wang and Edwin Sha and Chung, \{Jin Gyun\}",

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AU - Jiang, Yingtao

AU - Al-Sheraidah, Abdulkarim

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AU - Sha, Edwin

AU - Chung, Jin Gyun

PY - 2004/7

Y1 - 2004/7

N2 - The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

AB - The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

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M3 - 文章

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JF - IEEE Transactions on Circuits and Systems II: Express Briefs

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A Novel Multiplexer-Based Low-Power Full Adder

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Keywords

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