A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology

Liangjian Lyu; Yu Wang; Chixiao Chen; C. J. Richard Shi

doi:10.1145/3287624.3287757

A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology

Liangjian Lyu
, Yu Wang^*
, Chixiao Chen
, C. J. Richard Shi

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A low-voltage low-power 16-channel neural interface front-end IC for in-vivo neural recording applications is presented in this paper. A current reuse telescope amplifier is used to achieve better noise efficiency factor (NEF). Power efficiency factor (PEF) is further improved by reducing supply voltage with the proposed level-shifted feedback (LSFB) technique. The neural interface is fabricated in a 65 nm CMOS process. It operates under 0.6V supply voltage consuming 1.07 µW/channel. An input referred noise of 5.18 µV is measured, leading to a NEF of 2.94 and a PEF of 5.19 over 10 kHz bandwidth.

Original language	English
Title of host publication	ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	13-14
Number of pages	2
ISBN (Electronic)	9781450360074
DOIs	https://doi.org/10.1145/3287624.3287757
State	Published - 21 Jan 2019
Externally published	Yes
Event	24th Asia and South Pacific Design Automation Conference, ASPDAC 2019 - Tokyo, Japan Duration: 21 Jan 2019 → 24 Jan 2019

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	24th Asia and South Pacific Design Automation Conference, ASPDAC 2019
Country/Territory	Japan
City	Tokyo
Period	21/01/19 → 24/01/19

Access to Document

10.1145/3287624.3287757

Cite this

Lyu, L., Wang, Y., Chen, C., & Richard Shi, C. J. (2019). A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. In ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference (pp. 13-14). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3287624.3287757

Lyu, Liangjian ; Wang, Yu ; Chen, Chixiao et al. / A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 13-14 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{7d4a242b6be943b8afe200b6241caddf,

title = "A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology",

abstract = "A low-voltage low-power 16-channel neural interface front-end IC for in-vivo neural recording applications is presented in this paper. A current reuse telescope amplifier is used to achieve better noise efficiency factor (NEF). Power efficiency factor (PEF) is further improved by reducing supply voltage with the proposed level-shifted feedback (LSFB) technique. The neural interface is fabricated in a 65 nm CMOS process. It operates under 0.6V supply voltage consuming 1.07 µW/channel. An input referred noise of 5.18 µV is measured, leading to a NEF of 2.94 and a PEF of 5.19 over 10 kHz bandwidth.",

author = "Liangjian Lyu and Yu Wang and Chixiao Chen and \{Richard Shi\}, \{C. J.\}",

note = "Publisher Copyright: {\textcopyright} 2019 Copyright is held by the owner/author(s).; 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019 ; Conference date: 21-01-2019 Through 24-01-2019",

year = "2019",

month = jan,

day = "21",

doi = "10.1145/3287624.3287757",

language = "英语",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "13--14",

booktitle = "ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference",

address = "美国",

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Lyu, L, Wang, Y, Chen, C & Richard Shi, CJ 2019, A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. in ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 13-14, 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, 21/01/19. https://doi.org/10.1145/3287624.3287757

A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. / Lyu, Liangjian; Wang, Yu; Chen, Chixiao et al.
ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 13-14 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A low-voltage low-power 16-channel neural interface front-end IC for in-vivo neural recording applications is presented in this paper. A current reuse telescope amplifier is used to achieve better noise efficiency factor (NEF). Power efficiency factor (PEF) is further improved by reducing supply voltage with the proposed level-shifted feedback (LSFB) technique. The neural interface is fabricated in a 65 nm CMOS process. It operates under 0.6V supply voltage consuming 1.07 µW/channel. An input referred noise of 5.18 µV is measured, leading to a NEF of 2.94 and a PEF of 5.19 over 10 kHz bandwidth.

AB - A low-voltage low-power 16-channel neural interface front-end IC for in-vivo neural recording applications is presented in this paper. A current reuse telescope amplifier is used to achieve better noise efficiency factor (NEF). Power efficiency factor (PEF) is further improved by reducing supply voltage with the proposed level-shifted feedback (LSFB) technique. The neural interface is fabricated in a 65 nm CMOS process. It operates under 0.6V supply voltage consuming 1.07 µW/channel. An input referred noise of 5.18 µV is measured, leading to a NEF of 2.94 and a PEF of 5.19 over 10 kHz bandwidth.

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DO - 10.1145/3287624.3287757

M3 - 会议稿件

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T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

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Lyu L, Wang Y, Chen C, Richard Shi CJ. A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. In ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 13-14. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/3287624.3287757

A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology

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